MT5931 802.11n platform (2.4GHz) Technical Brief

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MT5931 802.11n platform (2.4GHz)
Technical Brief
Version:
Release date:
1.0
September 8, 2014
Specifications are subject to change without notice.
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction of this information in whole or in part is strictly prohibited.
MT5931
802.11n platform (2.4GHz) Technical Brief
Table of Contents
1
System Overview .................................................................................................. 4
1.1
1.2
1.3
1.4
2
Product Descriptions ........................................................................................... 6
2.1
2.2
2.3
3
PMU Descriptions .................................................................................................................... 17
Absolute Maximum Ratings .................................................................................................... 17
Recommended Operating Range ............................................................................................ 18
PMU Electrical Characteristics................................................................................................18
XOSC32..................................................................................................................................... 19
DC Electrical Characteristics for 2.8 Volts Operation........................................................... 20
DC Electrical Characteristics for 1.8 Volts Operation ............................................................ 21
Interface ............................................................................................................ 22
4.1
4.2
4.3
5
Pin Descriptions ........................................................................................................................ 6
Package Information ................................................................................................................ 11
Ordering Information .............................................................................................................. 16
Electrical Characteristics .................................................................................... 17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
General Descriptions................................................................................................................. 4
Features ..................................................................................................................................... 4
Applications ................................................................................................................................5
Block Diagram ............................................................................................................................5
Host Interface (HIF) ............................................................................................................... 22
EEPROM Interface................................................................................................................... 31
EFUSE Function...................................................................................................................... 33
Radio Characteristics ......................................................................................... 34
5.1
5.2
Tx/Rx Specifications ............................................................................................................... 34
Current Consumption ..............................................................................................................37
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 2 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Lists of Tables and Figures
Table 1. Pin descriptions .............................................................................................................................10
Table 2. OSC/XTAL frequency selection ....................................................................................................10
Table 5. Absolute maximum ratings ...........................................................................................................18
Table 6. Recommended operating range ...................................................................................................18
Table 7. PMU characteristics ...................................................................................................................... 19
Figure 1. MT5931 block diagram ..................................................................................................................5
Figure 2. MT5931 TFBGA top marking ...................................................................................................... 11
Figure 3. MT5931 TFBGA POD (a) ............................................................................................................. 12
Figure 4. MT5931 TFBGA POD (b)............................................................................................................. 13
Figure 5. MT5931 WLCSP marking ............................................................................................................ 14
Figure 6. MT5931 WLCSP POD (a) ............................................................................................................ 14
Figure 7. MT5931 WLCSP POD (b) ............................................................................................................ 15
Figure 8. MT5931 WLCSP POD (c) ............................................................................................................ 15
Figure 9. MT5931 WLCSP POD (d) ............................................................................................................ 16
Figure 10. Block diagram of XOSC32 ......................................................................................................... 19
Figure 11. Signal connections to one 4-bit SDIO card and host interrupt............................................... 22
Figure 12. Bus signal levels ........................................................................................................................ 23
Figure 13. Bus timing diagram (default) ................................................................................................... 23
Figure 14. High-speed timing diagram...................................................................................................... 24
Figure 15. T-Mode SPI protocol ................................................................................................................. 25
Figure 16. M-Mode SPI protocol................................................................................................................ 26
Figure 17. eHPI8 single write access ..........................................................................................................27
Figure 18. eHPI8 single read access ...........................................................................................................27
Figure 19. eHPI8 burst write access (data port) ........................................................................................27
Figure 20. eHPI8 burst read access (data port)........................................................................................ 28
Figure 21. eHPI16 single write access........................................................................................................ 28
Figure 22. eHPI16 single read access ........................................................................................................ 28
Figure 23. eHPI16 burst write access (data port) ..................................................................................... 29
Figure 24. eHPI16 burst read access (data port) ...................................................................................... 29
Figure 25. eHPI write cycle timing diagram ............................................................................................. 29
Figure 26. eHPI read cycle timing diagram .............................................................................................. 30
Figure 27. EEPROM configuration ............................................................................................................. 31
Figure 28. EEPROM CRC checksum diagram .......................................................................................... 32
Figure 29. EEPROM interface connection ................................................................................................ 32
Figure 30. EEPROM data timing............................................................................................................... 32
Figure 31 2.4GHz Receiver Specifications................................................................................................. 34
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 3 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
1 System Overview
1.1 General Descriptions
MT5931 is a Wi-Fi device which includes
•
802.11 b/g/n
•
PA
•
LNA
•
TR-Switch
MT5931 provides the best and most convenient connectivity functions. MT5931 implements advanced
and sophisticated radio coexistence algorithms and hardware mechanisms. The enhanced overall
quality for simultaneous voice, data, and audio/video transmission on mobile phone and Tablet PC
can be achieved. The small package size with low power consumption reduces the PCB layout area.
1.2 Features
•
Embedded RISC core for better system level management
•
Coexistence: IEEE 802.15.2 external three-wire coexistence scheme to support additional wireless
technologies such as 3G, GPS and WiMAX
•
Self calibration.
•
Integrated switching regulator enables direct connection to battery.
•
Best-in-class current consumption performance
•
Intelligent BT/WLAN coexistence scheme that goes beyond PTA signaling (for example, transmit
window and duration that take into account of protocol exchange sequence, frequency, etc.)
•
TFBGA (5.1x5.3mm2) and WLCSP (2.93x3.17mm2) packages
•
2.4GHz single stream 802.11 b/g/n MAC/BB/RF
•
802.11 d/h/k compliant
•
Security: WFA WPA/WPA2 personal, WPS2.0, WAPI (hardware)
•
QoS: WFA WMM, WMM PS
•
Supports 802.11n optional features: STBC, A-MPDU, Blk-Ack, RIFS, MCS Feedback, 20/40 MHz
coexistence (PCO), unscheduled PSMP
•
Supports 802.11w protected managed frames
•
Supports Wi-Fi Direct
•
Interface: SDIO 2.0 (4-bit & 1-bit), SPI(TFBGA only) , EHPI-8/16 (TFBGA only)
•
Per packet Tx power control
© 2014 MediaTek Inc.
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 4 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
1.3 Applications
•
Smart phones
•
Tablet PC
•
Mobile Internet Device (MID)
•
Portable Navigation Device (PND)
•
Portable Media Player (PMP)
•
Portable gaming devices
1.4 Block Diagram
Figure 1. MT5931 block diagram
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 5 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
2 Product Descriptions
2.1 Pin Descriptions
Symbol
WLCSP TFBGA
bump
ball
Description
PU/PD
I/O
Power ground pin
CGND
F6
F4
Ground
NA
VSS
CGND
G6
F6
Ground
NA
VSS
PAD_VDDK
E5
G4
1.2V core power
NA
VDD
PAD_VDDK
G6
1.2V core power
NA
VDD
PAD_VDDK
G7
1.2V core power
NA
VDD
H1
1.8/2.8V host interface I/O power
NA
VDD
CGND
F7
Ground
NA
VSS
CGND
K1
Ground
NA
VSS
K10
1.8 / 2.8V I/O power
NA
VDD
DVDDIO2
J7
1.8/2.8V host interface or PTA I/O
power
NA
VDD
DVDDIO1
K7
1.8/2.8V PTA I/O power
NA
VDD
DVDDIO3
DVDDIO0
F3
G1
PMU
GND_REF
B7
B1
Ground
NA
OUT_FB
C7
C3
Buck feedback
NA
AVDD16_CLDO
C8
C2
CLDO feedback
NA
CLDO
B8
C1
CLDO 1.2V output
NA
REF
A8
A1
Bandgap reference point
NA
AVDD43_REF
A7
A2
4.3V reference point
NA
AGND43_SMPS
B6
B3
Ground
NA
LXBK
A6
A3
Buck feedback
NA
AVDD43_SMPS
B5
A4
Buck power
NA
PALDO
A5
A5
PALDO output
NA
GND_PALDO
C5
C5
Ground
NA
PALDO_FB
C6
E5
PALDO remote sense feedback
NA
PAD_EN
D7
B5
PMU enable from host
NA
I
X32K_IN
D6
D1
RTC 32 kHz clock input
NA
I
AVDDRTC
D8
D3
RTC power
NA
VDD
D4
RTC ground
NA
VSS
D2
RTC 32K output
NA
O
RTC
AVSSRTC
X32K_OUT
D5
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 6 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
WLCSP TFBGA
bump
ball
Description
PU/PD
I/O
C4
A6
XO power
NA
VDD
PAD_ICAL_EXTR
F10
External ICAL input
NA
I
TRX_QN
E9
TRX Q signal
NA
I/O
TRX_QP
E8
TRX Q signal
NA
I/O
TRX_IN
E7
TRX I signal
NA
I/O
TRX_IP
E6
TRX I signal
NA
I/O
RF
AVDD33_XO
AVDD16_LF
D1
E10
LF power
NA
VDD
AVSS16_WF
C2
D6
Ground
NA
VSS
AVSS16_WF
D2
D7
Ground
NA
VSS
AVDD16_TRX
C1
D10
TRX power
NA
VDD
AVSS16_WF
B3
D9
Ground
NA
VSS
TRX_IO_N
B1
C10
TRX IO signal
NA
I/O
AVSS33_PA
A2
A10
Ground
NA
VSS
AVSS33_PA
B2
B9
Ground
NA
VSS
TRX_IO_P
A1
B10
TRX IO signal
NA
I/O
AVDD33_TX
A3
A9
WLAN power
NA
VDD
AVSS33_PA
C9
Ground
NA
VSS
AVSS16_VCO
B8
Ground
NA
VSS
A8
SX power
NA
VDD
C6
Ground
NA
VSS
A4
A7
XTAL/OSC input
NA
I
FSOURCE
F7
E1
eFuse power pin
NA
VDD
WI-FI_INT_B
F5
E2
WI-FI_INT_B: Wi-Fi component
interrupt output
None/SW
O
J6
eHPI_DAT15: eHPI data bus bit 15
None/SW
I/O
WX_REQ: WiMAX co-existence
PTA interface
None/SW
I
eHPI_DAT14: eHPI data bus bit 14
None/SW
I/O
WX_INFO: WiMAX co-existence
PTA interface
None/SW
I
eHPI_DAT13: eHPI data bus bit 13
None/SW
I/O
WX_NO_GRANT: WiMAX
co-existence PTA interface
None/SW
O
AVDD16_SX
C3
AVSS16_WF
OSC_IN
Digital
D15
D14
D13
J5
K6
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
WLCSP TFBGA
bump
ball
D12
H6
D11
H5
D10
H4
D9
J4
D8
K4
D7
E3
D6
G3
D5
G2
D4
D3
D2
D1
D0
G1
E8
E7
E6
F8
K2
H2
J3
H3
Description
PU/PD
I/O
eHPI_DAT12: eHPI data bus bit 12
None/SW
I/O
BT_FREQ: BT co-existence PTA
interface
None/SW
I
eHPI_DAT11: eHPI data bus bit 11
None/SW
I/O
BT_ACT: BT co-existence PTA
interface
None/SW
I
eHPI_DAT10: eHPI data bus bit 10
None/SW
I/O
WLAN_ACT: BT co-existence PTA None/SW
interface
O
eHPI_DAT9: eHPI data bus bit 9
None/SW
I/O
GPIO0_16: GPIO0_16 in/out
None/SW
I/O
eHPI_DAT8: eHPI data bus bit 8
None/SW
I/O
GPIO0_17: GPIO0_17 in/out
None/SW
I/O
eHPI_DAT7: eHPI data bus bit 7
None/SW
I/O
EEDO: EEPROM interface
None/SW
I
GPIO0_18: GPIO0_18 in/out
None/SW
I/O
eHPI_DAT6: eHPI data bus bit 6
None/SW
I/O
EEDI: EEPROM interface
None/SW
O
GPIO0_19: GPIO0_19 in/out
None/SW
I/O
eHPI_DAT5: eHPI data bus bit 5
None/SW
I/O
EECS: EEPROM interface
None/SW
O
GPIO0_20: GPIO0_20 in/out
None/SW
I/O
eHPI_DAT4: eHPI data bus bit 4
None/SW
I/O
EESK: EEPROM interface
None/SW
O
GPIO0_21: GPIO0_21 in/out
None/SW
I/O
eHPI_DAT3: eHPI data bus bit 3
None/SW
I/O
SDIO_DAT3: SDIO data bus bit 3
PU
I/O
GPIO0_22: GPIO0_22 in/out
None/SW
I/O
eHPI_DAT2: eHPI data bus bit 2
None/SW
I/O
SDIO_DAT2: SDIO data bus bit 2
None/SW
I/O
GPIO0_23: GPIO0_23 in/out
None/SW
I/O
eHPI_DAT1: eHPI data bus bit 1
None/SW
I/O
SDIO_DAT1: SDIO data bus bit 1
None/SW
I/O
GPIO0_24: GPIO0_24 in/out
None/SW
I/O
eHPI_DAT0: eHPI data bus bit 1
None/SW
I/O
SDIO_DAT0: SDIO data bus bit 1
None/SW
I/O
SPI_DIN: SPI interface DIN
None/SW
I
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 8 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
WLCSP TFBGA
bump
ball
Description
PU/PD
I/O
A0
G7
eHPI_A0: eHPI interface A0
None/SW
I
SDIO_CMD: SDIO interface CMD
None/SW
I/O
SPI_DOUT: SPI interface DOUT
None/SW
O
eHPI_CSN: eHPI interface CS_N
None/SW
I
GPIO0_27: GPIO0_27 in/out
None/SW
I/O
SPI_CS: SPI interface CS
None/SW
I
eHPI_WEN: eHPI interface WE_N
None/SW
I
GPIO0_28: GPIO0_28 in/out
None/SW
I/O
SPI_MODE_SEL: SPI interface
MODE_SEL
None/SW
I
eHPI_OEN: eHPI interface OE_N
None/SW
I
SDIO_CLK: SDIO interface
SD_CLK
None/SW
I
SPI_CLK: SPI interface SPI_CLK
None/SW
I
RF_I_CAL: Analog pin
NA
I
OSC_EN: OSC enable in
co-clocking platform
None/SW
O
CS_N
F3
WE_N
OE_N
RF_I_CAL
F2
G8
J2
D4
OSC_EN
F9
GPIO_0
G10
GPIO_1
BT_PRI
J1
H9
G4
H7
ICAP_TRIG_EXT: External trigger None/SW
event for internal capture debugging
I
OSC_EN: OSC enable in
co-clocking platform
O
None/SW
ICAP_TRIG_EXT: External trigger None/SW
event for internal capture debugging
I
ANTSEL_0: Antenna selection #0
PD/SW
O
UART_DBG_RX: UART debug
RXD
None/SW
I
GPIO0_8: GPIO0_8 in/out
None/SW
I/O
ANTSEL_1: Antenna selection #1
PD/SW
O
UART_DBG_TX: UART debug
TXD
None/SW
O
GPIO0_0: GPIO0_0 in/out
None/SW
I/O
BT_PRI: BT co-existence PTA
interface
PD
I/O
GPIO0_9: GPIO0_9 in/out
PD
I/O
ANTSEL_0
G2
K8
ATNSEL_0: Antenna selection #0
PD/SW
O
ANTSEL_1
G3
J8
ATNSEL_1: Antenna selection #1
PU/SW
O
ANTSEL_2
E1
G9
EESK: EEPROM interface
PD/SW
O
WLAN_ACT: BT co-existence PTA None/SW
interface
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
O
Page 9 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
WLCSP TFBGA
bump
ball
Description
PU/PD
I/O
ANTSEL_3
E2
EEDI: EEPROM interface
PD/SW
O
GPIO0_7: GPIO0_7 in/out
None/SW
I/O
EECS: EEPROM interface
None/SW
O
UART_DBG_TX: UART debug
TXD
None/SW
O
EEDO: EEPROM interface
PD/SW
I
UART_DBG_RX: UART debug
RXD
None/SW
I
ICAP_TRIG_EXT: External trigger None/SW
event for internal capture debugging
I
WLAN_ACT: BT co-existence PTA None/SW
interface
O
EXT_INT_B: External interrupt
input from Host
None/SW
I
UART_DBG_TX
F8
E3
UART_DBG_RX
J10
F1
EXT_INT_B
H10
F2
H8
XTEST
F4
J9
Test mode enable
PD
I
SYSRST_B
E4
K9
External system reset active low
PU
I
Table 1. Pin descriptions
2.1.1 Strapping Table
XTAL_SEL[0]
(ANTSEL_0)
0
XTAL_SEL[1]
(ANTSEL_1)
0
1
XTAL_SEL[2]
(GPIO_1)
0
0
Description
24 MHz
0
19.2 MHz
0
1
0
26 MHz (default)
1
1
0
Reserved
0
0
1
Reserved
1
0
1
52 MHz
0
1
1
Reserved
1
1
1
Reserved
Table 2. OSC/XTAL frequency selection
WLCSP package only supports 26 MHz.
SLOW_SRC
(GPIO_0)
Note
1
Internal
0
External
Table 3. Slow clock source selection
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 10 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
WLCSP package use SW select Slow clock source.
OSC_SRC
【WI-FI_INT_B】
Note
0
OSC / Co-clocking
1
XTAL
Table 4. Clock source selection
HOST[0]
(ANTSEL_2)
0
HOST[1]
(ANTSEL_3)
0
Note
1
0
eHPI-16
0
1
SPI
1
1
SDIO
eHPI-8
Table 5. Host interface selection
WLCSP package only supports SDIO.
2.2 Package Information
2.2.1 TFBGA Packaging
Figure 2. MT5931 TFBGA top marking
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 11 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 3. MT5931 TFBGA POD (a)
Dimension in mm.
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 12 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 4. MT5931 TFBGA POD (b)
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 13 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
2.2.2 WLCSP Packaging
Figure 5. MT5931 WLCSP marking
Figure 6. MT5931 WLCSP POD (a)
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 14 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 7. MT5931 WLCSP POD (b)
Figure 8. MT5931 WLCSP POD (c)
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 15 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 9. MT5931 WLCSP POD (d)
2.3 Ordering Information
Part number
MT5931A/B
MT5931P/B
Package
TFBGA
WLCSP
© 2014 MediaTek Inc.
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Page 16 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
3 Electrical Characteristics
3.1 PMU Descriptions
MT5931 integrates the Power Management Unit (PMU) which generates power supplies required by
the internal circuitry from the battery.
PMU mainly contains Low Dropout Regulators (LDOs), buck converter and control circuits such as
Under-Voltage Lockout (UVLO), thermal protection and power-on/off sequencer.
3.1.1 PALDO
PALDO converts the battery input to a 3.3V supply for the use of Wi-Fi RF PA circuits. It is optimized
for the given functions by balancing the quiescent current, dropout voltage, line/load regulation,
ripple rejection and output noise.
3.1.2 CLDO
One CLDO is integrated in PMU to supply digital core. It converts 1.8V input to 1.2V output which is
suited for the digital circuits. The input is typically connected to the buck’s output.
3.1.3 Buck Converter
The regulator is a DC-DC step-down converter (buck converter) which produces programmable power
supply from the battery input. Typically it supplies power for the core LDO and RF circuits. The buck
converter is optimized for high efficiency, low EMI and low quiescent current.
3.2 Absolute Maximum Ratings
Symbol
DVDDIO0
DVDDIO1
DVDDIO2
DVDDIO3
(VIO_HOST)
DVDD
AVDD_CLDO
AVDD28_*
Parameter
Rating
Unit
1.8V or 2.8V digital power supply
-0.3 to 3.6
V
1.8V or 2.8V SDIO digital IO power supply
-0.3 to 3.6
V
Digital 1.2V power supply
Internal CLDO power supply
-0.3 to 3.6
-0.3 to 3.6
V
V
RF power supply
-0.3 to 3.6
V
AVDD13_*
RF power supply
-0.3 to 1.8
V
AVDD_SMPS
BUCK and PALDO power supply
-0.3 to 4.7
V
AVDD33_*
© 2014 MediaTek Inc.
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Page 17 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
Parameter
Rating
Unit
AVDD_MISC
PMU power supply
-0.3 to 4.7
V
TSTG
Storage temperature
-45 to +135
°C
Table 3. Absolute maximum ratings
3.3 Recommended Operating Range
Symbol
DVDDIO0
DVDDIO1
DVDDIO2
DVDDIO3
DVDD
AVDD13_*
AVDD28_*
AVDD33_*
AVDD_SMPS
AVDD_MISC
Tambient
Parameter
Min.
Typ,.
Max.
Unit
2.8V digital power supply
2.0
2.8
3.6
V
1.8V digital power supply
1.6
1.8
2.0
V
1.08
1.28
2.66
3.14
2.9
2.3
-40
1.2
1.35
2.8
3.3
3.8
3.8
25
1.32
1.4
2.94
3.46
4.3
4.3
85
V
V
V
V
V
V
°C
Max.
Unit
Digital core power supply
RF power supply
RF power supply
RF power supply
BUCK and PALDO power supply
PMU power supply
Ambient temperature
Table 4. Recommended operating range
3.4 PMU Electrical Characteristics
3.4.1 PMU Characteristics
Parameter
Conditions
Min.
Typ.
PMU_EN = 0: Shut down current
VBAT < 2.3V
2.3V < VBAT < 4.3V
VBAT = 2.3V
VBAT = 3.8V
PMU_EN = 1: Quiescent current
All outputs on
VBAT = 4.2V
PALDO off, CORE LDO and buck
VBAT = 4.2V
converter on
15
20
μA
μA
100
μA
56
μA
2.25
2.15
V
V
Under Voltage Lock-Out (UVLO)
Under voltage rising threshold
Under voltage falling threshold
PMU_EN voltage level
High voltage
Low voltage
1.4
1.0
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V
V
Page 18 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Parameter
Conditions
Min.
Typ.
Thermal shutdown
Threshold
Hysteresis
LDO enable response time
SMPS voltage
Output voltage (V_BUCK)
Max.
Unit
150
40
250
°C
°C
μs
1.65
V
1.2
V
3.3
V
Digital core voltage
Output voltage (V_D)
WLAN PA voltage
Output voltage (V_PALDO)
Table 5. PMU characteristics
3.5 XOSC32
3.5.1 Block Descriptions
The low-power 32-kHz crystal oscillator, XOSC32, is designed to work with an external piezoelectric
32.768 kHz crystal and a load composed of two functional capacitors. See the figure below.
Figure 10. Block diagram of XOSC32
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MT5931
802.11n platform (2.4GHz) Technical Brief
3.5.2 Function Specification of XOSC32
Symbol
Parameter
Min.
AVDDRTC
Analog power supply
Tosc
Start-up time
Dcyc
Duty cycle
Typ.
1
Max.
2.8
30
50
Current consumption
Unit
3
V
1
Sec.
70
%
μA
5
Table 8. Function specification of XOSC32
3.5.3 Recommendations for Crystal Parameters for XOSC32
Symbol
Parameter
F
Frequency range
GL
Drive level
∆f/f
Frequency tolerance
ESR
Series resistance
50
KΩ
C0
Static capacitance
1.6
pF
12.5
pF
CL
1
0F
Min.
Typ.
Max.
Unit
32,768
Hz
5
uW
ppm
+/- 20
Load capacitance
6
Table 9. Recommended parameters of the 32 kHz crystal
3.6 DC Electrical Characteristics for 2.8 Volts Operation
Symbol
Parameter
Conditions
VIL
VIH
LVTTL
VOL
Input low voltage
Input high voltage
Schmitt trigger negative going
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
VOH
RPU
RPD
VTVT+
Min.
Max.
Unit
-0.28
2.0
0.6
3.08
V
V
0.68
1.36
V
1.36
1.7
V
|IOL|=1.6~14 mA
-0.28
V
Output high voltage
|IOH|=1.6~14 mA
2.4
Input pull-up resistance
Input pull-down resistance
PU=high, PD=low
PU=low, PD=high
40
40
0.4
VDD28 +
0.28
190
190
LVTTL
V
KΩ
KΩ
Table 10. 2.8V DC descriptions
1
CL is the parallel combination of C1 and C2 in the block diagram.
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MT5931
802.11n platform (2.4GHz) Technical Brief
3.7 DC Electrical Characteristics for 1.8 Volts Operation
Symbol
Parameter
VIL
VIH
VOL
Input lower voltage
Input high voltage
Schmitt trigger negative going
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
VOH
RPU
RPD
VTVT+
Conditions
Min.
Max.
Unit
-0.18
1.5
0.4
1.98
V
V
0.44
0.88
V
0.88
1.1
V
|IOL|=1.6~14 mA
-0.18
V
Output high voltage
|IOH|=1.6~14 mA
1.4
Input pull-up resistance
Input pull-down resistance
PU=high, PD=low
PU=low, PD=high
40
40
0.4
VDD18 +
0.18
190
190
LVTTL
LVTTL
V
KΩ
KΩ
Table 11. 1.8V DC description
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Page 21 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
4 Interface
4.1 Host Interface (HIF)
MT5931 HIF module provides 3 interfaces to connect to the host, which are one SDIO card interface,
one SPI interface and one eHPI interface.
SDIO provides high-speed data I/O with low power consumption for mobile electronic devices.
During normal initialization and interrogation by the SDIO host, the SDIO client identifies itself as an
SDIO card. The host software obtains the card information in a tuple (linked list) format and
determines if the I/O functions of the card are acceptable to be activated.
For the SDIO bus driver provided by OS, it simply maintains a single First-In-First-Out queue for
processing the SDIO bus requested from different client drivers. For the client driver operated on the
OS, its function is registered to OS and will be invoked by OS in its thread priority.
In the assumption of the host interface is the performance limitation for the functions attached to the
HIF. Several bus access management approaches can be taken toward differentiating the high and low
priority traffic. However, the performance limitation may also exist under different user scenarios.
4.1.1 Signal Pins
Host
MT5931
SD 1 _CLK
SD Host
SD 1 _CMD
SD 1 I/O Card
SD 1 _DAT 0~3
eHPI Host
CE_N
WR_
N
RD_N
A0
DATA0~15
Host IRQ /EINT
WI-FI_INT_B
EXT_INT_B
eHPI Slave
Interrupt Control
Figure 11. Signal connections to one 4-bit SDIO card and host interrupt
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MT5931
802.11n platform (2.4GHz) Technical Brief
4.1.2 SDIO Timing Waveform
V
VDD
Output
high level
VOH
VIH
undefined
VIL
Output
low level
VOL
VSS
t
Figure 12. Bus signal levels
Parameter
Symbol
Min.
Max.
Unit
Conditions
Output high voltage
VOH
0.75*VDD
V
IOH = -100uA
VDD min
Output low voltage
VOL
0.125*VDD
V
IOL = 100uA
VDD min
Input high voltage
VIH
0.625*VDD
VDD+0.3
V
Input low voltage
VIL
Vss-0.3
0.25*VDD
V
Table 13. Bus signal voltage
fpp
0.7
0.2
tWL
tWH
VIH
Clock
VIL
tTLH
tTHL
tISU
tIH
VIH
Input
VIL
VOH
Output
VOL
tODLY(max)
tODLY(min)
Shaded ares are not valid
Figure 13. Bus timing diagram (default)
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MT5931
802.11n platform (2.4GHz) Technical Brief
Parameter
Symbol
Min.
Max.
Unit
Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency data transfer
mode
Clock frequency identification
mode
fPP
0
25
MHz
CCARD ≤ 10 pF (1 card)
fOD
0/100
400
kHz
CCARD ≤ 10 pF (1 card)
Clock low time
tWL
10
ns
CCARD ≤ 10 pF (1 card)
Clock high time
tWH
10
ns
CCARD ≤ 10 pF (1 card)
Clock rise time
tTLH
10
ns
CCARD ≤ 10 pF (1 card)
Clock fall time
tTHL
10
ns
CCARD ≤ 10 pF (1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
5
ns
CCARD ≤ 10 pF (1 card)
Input hold time
tIH
5
ns
CCARD ≤ 10 pF (1 card)
Outputs CMD, DAT (referenced to CLK)
Output delay time during data
transfer mode
Output delay time during
identification mode
tOLDY
0
14
ns
CL ≤ 10 pF (1 card)
tOLDY
0
50
ns
CL ≤ 10 pF (1 card)
Table 14. Bus timing parameter values (default)
fpp
0.7
0.2
50%VDD
tWL
tWH
VIH
Clock
tTLH
tTHL
tISU
VIL
tIH
VIH
Input
VIL
VOH
Output
VOL
tODLY(max)
tOH
Figure 14. High-speed timing diagram
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MT5931
802.11n platform (2.4GHz) Technical Brief
Parameter
Symbol
Min.
Max.
Unit
Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency data transfer mode
fPP
0
Clock low time
tWL
Clock high time
tWH
Clock rise time
tTLH
Clock fall time
tTHL
50
MHz
CCARD ≤ 10 pF (1 card)
7
ns
CCARD ≤ 10 pF (1 card)
7
ns
CCARD ≤ 10 pF (1 card)
3
ns
CCARD ≤ 10 pF (1 card)
3
ns
CCARD ≤ 10 pF (1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
6
ns
CCARD ≤ 10 pF (1 card)
Input hold time
tIH
2
ns
CCARD ≤ 10 pF (1 card)
ns
CL ≤ 10 pF (1 card)
ns
CL ≥ 10 pF (1 card)
pF
1 card
Outputs CMD, DAT (referenced to CLK)
Output delay time during data
transfer mode
tOLDY
Output hold time
14
tOH
2.5
Total system capacitance for each
CL
40
line*
*In order to satisfy serve timing, the host shall drive only one card.
Table 15. High-speed timing parameter values
4.1.3 SPI Timing Waveform
MT5931 supports SPI with T-mode and M-mode, 8-/16-/32-bit mode and big/little endian.
Select pin (SPI_MODE_SEL)
Mode
0
1
M-Mode
T-Mode
Table 16. SPI mode selection
n-1
n-2
n-3
3
2
1
0
spi_clk
spi_cs
spi_din
msb
lsb
spi_dout
msb
lsb
T - mode
Figure 15. T-Mode SPI protocol
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MT5931
802.11n platform (2.4GHz) Technical Brief
n-1
n-2
n-3
3
2
1
0
spi_ clk
spi_cs
spi_din
msb
lsb
spi_dout
msb
lsb
M - mode
Figure 16. M-Mode SPI protocol
Tcss
Tclk
spi_clk
Tcr
Tcf
spi_cs
Tins
Tinh
spi_din
Tod
spi_dout
Symbol
Tclk
Tcr/Tcf
Tcss
Tins
Tinh
Tod
Parameter
SPI clock period
Clock Rise/Fall time
CS setup time
Din setup time
Din hold time
Dout output delay
Min.
40
Typ.
Max.
2.5
7.86
5
5
14
Unit
ns
ns
ns
ns
ns
ns
Note: This timing spec criterion is VIO = 1.8V. It will gain better performance if stronger VIO is set.
4.1.4 eHPI Timing Waveform
Use the strapping method in section 2.1.1 to set up eHPI-8 or eHPI-16. With eHPI-8 being selected,
we need 4 input control pins and 8 data pins, and with eHPI-16 being selected, we need 4 input
control pins and 16 data pins. However eHPI-16 can achieve almost twice the data rate for large
amount burst data access.
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MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 17. eHPI8 single write access
Figure 18. eHPI8 single read access
Figure 19. eHPI8 burst write access (data port)
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MT5931
802.11n platform (2.4GHz) Technical Brief
Figure 20. eHPI8 burst read access (data port)
CE_N
WE_N
RD_N
A0
D[15:0]
A[15:0]
Di[15:0]
Di[31:16]
Figure 21. eHPI16 single write access
CE_N
WE_N
RD_N
A0
D[15:0]
A[15:0]
Do[15:0]
Do[31:16]
Figure 22. eHPI16 single read access
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MT5931
802.11n platform (2.4GHz) Technical Brief
CE_N
WE_N
RD_N
A0
A
[15:0]
D[15:0]
D0
[15:0]
D0
[31:16]
D1
[15:0]
D1
[31:16]
Figure 23. eHPI16 burst write access (data port)
CE_N
WE_N
RD_N
A0
A
[15:0]
D[15:0]
D0
[15:0]
D0
[31:16]
D1
[23:16]
D1
[15:0]
Figure 24. eHPI16 burst read access (data port)
Twrh
Twrsu
Twrsu
Twrh
CS_N
Tidle
Tidle
Twr
Twr
WE_N
OE_N
A_0
D[15:0]
Tfall
Trise
Tdwrsu
Tdwrh
Address
Tdwrh
Tdwrsu
Input Data
Figure 25. eHPI write cycle timing diagram
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MT5931
802.11n platform (2.4GHz) Technical Brief
Symbol
Twr
Twrsu
Twrh
Tdwrsu
Tdwrh
Tidle
Trise/Tfall
Parameter
Write pulse width
CS_N vs WE_N setup time
CS_N vs WE_N hold time
Data & A_0 vs WE_N setup time
Data & A_0 vs WE_N hold time
Twice Access cycle space Time
Control & Data signals’ Rise/Fall time
Min
40
0
0
10
10
40
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
5
Table 17. Timing parameter of eHPI write cycle
Twrh
Twrsu
Trdsu
Trdh
CS_N
Tidle
Tidle
Twr
Tidle
WE_N
OE_N
Trd
Trise
Tfall
Tdis
Tdwrsu
D[15:0]
Tdh
Tdo
A_0
Tdwrh
Address
OutputData
Figure 26. eHPI read cycle timing diagram
Symbol
Twr
Twrsu
Twrh
Tdwrsu
Tdwrh
Tidle*
Trd
Trdsu
Trdh
Tdo
Tdh
Tdis
Trise/Tfall
Parameter
Write pulse width
CS_N vs WE_N setup time
CS_N vs WE_N hold time
Data & A_0 vs WE_N setup time
Data & A_0 vs WE_N hold time
Twice access cycle space Time
Read pulse width
CS_N vs OE_N setup time
CS_N vs OE_N hold time
Output data delay time
Output data hold time
Output disable time
Control & data signals’ rise/fall time
Min
40
0
0
10
10
40
40
0
0
Typ
Max
20
0
20
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 18. Timing parameter of eHPI read cycle
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Page 30 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
4.2 EEPROM Interface
4.2.1 EEPROM Controller Introduction
MT5931 supports 3-wire serial EEPROM of which the size range is from 128 to 2,048 bytes. The
controller operates on the 16-bit data protocol.
4.2.2 EEPROM Content
Word offset Byte offset
Content
Description
Default
0x00
0x00
Signature
EEPROM signature. MAC will
0x5931
automatically load the contents in
EEPROM to the corresponding registers if
the EEPROM signature is right after being
powered on; otherwise, the default values
will be used.
0x01~0x1B
0x002~0x036
MT5931.CIS0.
CISTPL_VERS_1
Content of MT5931 CIS0. Reserved 54
bytes for CISTPL_VERS_1 field.
0x1C
0x38
Checksum
Checksum (bit 15 ~ 8)
The check sum of data is from word offset
0x01 to word offset 0x1C. The sum from
byte 0x2 to byte 0x38 should be 0xFF.
Table 19. EEPROM content
ADR(Word)
0x00
Signature (16’h5931)
0x01~0x1B
0x1C
EEPROM
5931 CIS 0
CISTPL _VERS _1
Checksum
Figure 27. EEPROM configuration
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MT5931
802.11n platform (2.4GHz) Technical Brief
4.2.3 EEPROM Checksum Function
DO[7:0]
CheckSum
Checksum_error
DO[15:8]
0xFF
Figure 28. EEPROM CRC checksum diagram
After passing the signature of EEPROM controller check, the data will be read from EEPROM. The
checksum function will continue until the address reaches 0x1C.
4.2.4 EEPROM Interface Connection
3-Wire
Serial
EEPROM
EECS
EECS
EESK
EESK
EEDI
EEDI
EEDO
CLK_DC
MT6620
EEPROM
Controller
Figure 29. EEPROM interface connection
4.2.5 EEPROM Interface Timing
EECS
T = tSK
EESK
tDIS
tDIH
EEDI
tPD0
tPD1
EEDO
EECS
Figure 30. EEPROM data timing
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MT5931
802.11n platform (2.4GHz) Technical Brief
Description
Symbol
I2C serial clock
tSK
Data input setup time
tDIS
Data input hold time
tDIH
Data output delay to “0”
Data output delay to “1”
Min.
Max.
Unit
Notes
2500
ns
1
0.5T - 20
0.5T + 20
ns
0.5T - 20
0.5T + 20
ns
tPD0
500
ns
2
tPD1
500
ns
2
Table 20. EEPROM AC characteristics
Note:
1
It supports I2C fast mode up to 400 kHz.
2
The data output direction is from EEPROM slave to MT5931 master. This parameter depends on
the EEPROM device.
4.3 EFUSE Function
There are some EFUSE macros inside MT5931. EFUSE macro is a one-time-programming (OTP)
non-volatile memory used to store sensitive and important data. The EFUSE controller delivers
EFUSE status and re-initializes EFUSE macro. Users can program EFUSE via the EFUSE controller
by proper configuration and sequences.
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MT5931
802.11n platform (2.4GHz) Technical Brief
5 Radio Characteristics
5.1 Tx/Rx Specifications
5.1.1 2.4GHz Receiver Specifications
Figure 31 2.4GHz Receiver Specifications
Note: All specifications are measured at the antenna port unless otherwise specified.
Parameter
Description
Min.
Frequency range
2412
Rx sensitivity*
Rx sensitivity*
RX sensitivity*
BW = 20 MHz
Green field
800ns guard interval
Non-STBC
Rx sensitivity*
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps DSSS
11 Mbps DSSS
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS 0
MCS 1
MCS 2
MCS 3
MCS 4
MCS 5
MCS 6
MCS 7
MCS 0
Typ.
-96
-94
-91
-88.5
-92.5
-90.5
-89.5
-87
-84
-80
-76.5
-75
-92
-88.5
-86.5
-83.5
-80.5
-76
-74.5
-73
-89
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Max.
Unit
2,484
MHz
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Page 34 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
Parameter
BW = 40 MHz
Green field
800ns guard interval
Non-STBC
Maximum receive
level
Adjacent channel
rejection (30 MHz
offset)
Adjacent channel
rejection (25 MHz
offset)
Adjacent channel
rejection (25 MHz
offset)
Adjacent channel
rejection (25 MHz
offset), BW = 20 MHz
Adjacent channel
rejection (40 MHz
offset), BW = 40 MHz
Blocking level at RF
port (with external
filter)
Description
Min.
Typ.
Max.
Unit
-3
-3
-3
-3
-3
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
1 Mbps DSSS
40
dB
11 Mbps DSSS
40
dB
6 Mbps OFDM
37
dB
54 Mbps OFDM
25
dB
MCS 0
33
dB
MCS 7
18
dB
MCS 0
33
dB
MCS 7
18
dB
5
5
dBm
dBm
dBm
dBm
dBm
dBm
MCS 1
MCS 2
MCS 3
MCS 4
MCS 5
MCS 6
MCS 7
11 Mbps DSSS
6 Mbps OFDM
54 Mbps OFDM
MCS0
MCS7
848.8 MHz GSM
914.8 MHz GSM
1784.8 MHz GSM
1909.8 MHz GSM
1907.6 MHz WCDMA
1977.6 MHz WCDMA
-85.5
-83.5
-80.5
-77.5
-73
-71.5
-69.5
28
28
17
17
* Rx sensitivity degradation 1.5dB drops by WLCSP package type.
Table 21. 2.4GHz receiver specification
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MT5931
802.11n platform (2.4GHz) Technical Brief
5.1.2 2.4GHz Transmitter Specifications
Parameter
Frequency range
Description
Min.
2412
802.11b, 1~11 Mbps DSSS
802.11g, 6 ~ 54Mbps OFDM
802.11n, HT20 MCS0 ~ 7
802.11n, HT40 MCS0 ~ 7
Output power
Typ.
-
Max.
2,484
18.5
15.5
15.5
13.5
Unit
MHz
dBm
dBm
dBm
dBm
Tx power accuracy
±1.5
dB
Carrier suppression
30
dBc
Return loss
8
Transmitted power
Harmonic output
power
dB
76 ~ 108 MHz
776 ~ 794 MHz
869 ~ 960 MHz
925 ~ 960 MHz
1570 ~ 1,580 MHz
1,805 ~ 1,880 MHz
1,930 ~ 1,990 MHz
2,110 ~ 2,170 MHz
-143
-143
-143
-143
-143
-143
-143
-143
2nd harmonic
-44
3rd harmonic
-58
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/MH
z
dBm/MH
z
Table 22. 2.4GHz transmitter specification
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 36 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
5.2 Current Consumption
Note: All results are measured at the antenna port and VBAT is 3.6V.
Performance
Description
TYP
UNITS
Off
Rx active, BW40, HT40 MCS7
Rx active, BW20, all supported rates
Rx listen
Sleep mode
Rx power saving, DTIM = 1
TX HT40, [email protected]
15
53.8
48.9
36.2
74
0.54
164
μA
mA
mA
mA
μA
mA
mA
TX HT20, [email protected]
TX OFDM, [email protected]
TX CCK, [email protected]
170
187
190
mA
mA
mA
Table 23. WLAN 2.4GHz current consumption
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 37 of 38
MT5931
802.11n platform (2.4GHz) Technical Brief
ESD CAUTION
MT5931 is ESD (electrostatic discharge) sensitive device and may be damaged with ESD or spike
voltage. Although MT5931 is with built-in ESD protection circuitry, please handle with care to avoid
the permanent malfunction or the performance degradation.
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Page 38 of 38

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