System and method for using a real mode bios interface to read

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US005913058A
United States Patent [19]
[11]
Bonola
[45]
[54]
SYSTEM AND METHOD FOR USING A
REAL MODE BIOS INTERFACE TO READ
PHYSICAL DISK SECTORS AFTER THE
OPERATING SYSTEM HAS LOADED AND
BEFORE THE OPERATING SYSTEM
DEVICE DRIVERS HAVE LOADED
[75]
Patent Number:
Date of Patent:
5,913,058
Jun. 15, 1999
an executable program for execution on a dedicated I/O
processor before device drivers Which communicate With the
I/O processor have been loaded by an operating system. In
the preferred embodiment, the system comprises a plurality
of X86 processors coupled to a system memory. One of the
X86 processors is designated as a dedicated I/O processor. A
storage device stores an operating system for execution on
the remaining processors, an executable program for execut
Inventor: Thomas J. Bonola, Tomball, Tex.
ing on the dedicated I/O processor, such as a real-time
kernel, and a device driver Which is operable to execute on
[73] Assignee: Compaq Computer Corp.
the remaining processors and to communicate With the
[21]
[22]
Appl' NO': 08/941’623
Filed:
Sep. 30, 1997
real-time kernel executing on the I/O processor to perform
U0 operations on an I/O device. The storage device also
[51]
[52]
Int. Cl. ............................. .. G06F 9/06, G06F 13/00
U..S. Cl. ........................................... .. 395/652, 395/821
System executing on a ?rst of the remaining processors early
in the process of booting the Operating System The loader
[58]
Field of Search ................................... .. 395/651, 652,
program executing on the ?rst processor Creates a real mode
6
_
stores a loader program Which is loaded by the operating
395/653> 712> 200~5> 200~52> 200-51
_
[56]
interface in order to sWitch the ?rst processor to real mode
so that a real mode code portion of the loader can execute
References Clted
BIOS INT13 disk requests to read the real-time kernel from
Us PATENT DOCUMENTS
the storage device. Creating the real mode interface com
prises saving the protected mode state of the ?rst processor
5,291,585
3/1994 Sato et al. ............................. .. 395/500
2388?“ 2/1995 Chill?‘ et a1‘
s’ggg’ 5:133
‘ggn?gns et a '
392/252
4632
5’748’980
395/828
5/1998 Lipe et
""""" "
Primary Examiner—Kevin A. Kriess
Attorney, Agent, or Firm—Kevin L. Daffer; Conley, Rose &
Tayon
[57]
and of the System’S interrupt Control logic After Saving the
states of the ?rst processor and interrupt control logic, the
loader program programs the interrupt control logic to
simulate a real mode environment. The loader program also
provides a “tiled mapping” of memory addresses such that
the transition may be made from real mode to protected
mode and vice versa to facilitate the x86 processor real mode
and protected mode physical address computation differ
ences.
ABSTRACT
Asystem and method for using real mode BIOS calls to load
|
29 Claims, 6 Drawing Sheets
first processor switches to protected mode
t/_
100
| first processor loads host operating system into system memorygr 102
V
|
first processor loads lOP loacer driver into system memory
K 104
| ?rst processor reserves chunk of system memory in lower 1MB r 106
[
first processor creates real mode interface
t/_
108
l
?rst processor loads lOP kernel into system memory by switching
into real mode and issuing INT13 calls then switching back to
protected mode
I
first processor destroys real mode interface
I
first processor spawns off IOP kernel onto second processor
/-110
If
112
|f 114
first processor loads device driver, which is able to issue requests
116
to the IOP kernel executing on the second processor, into system /_
memory
U.S. Patent
Jun. 15,1999
Sheet 2 of6
first processor switches to protected mode
5,913,058
/_ 100
$
102
l
l
r104
$
108
first processor loads host operating system into system memory
first processor loads lOP loaderdriver into system memory
first processor reserves chunk of system memory in lower 1MB /_ 106
first processor creates real mode interface
J,
?rst processor loads IOP kernel into system memory by switching
into real mode and issuing |NTt3 calls then switching back to
110
/_
protected mode
l
first processor destroys real mode interface
l
first processor spawns off IOP kernel onto second processor
/_ 112
/_ 114
first processor loads device driver, which is able to issue requests
116
to the IOP kernel executing on the second processor, into system /_
memory
FIG. 2
U.S. Patent
Jun. 15,1999
Sheet 3 of6
load IOP kernel into system memory by switching into
real mode, issuing lNTl3 calls, and switching back
to protected mode
5,913,058
110
Open the image file
/— 160
read the image file header
/_ 162
l
scan through sections in header; for each code or initialized
data section load section into system memory; for other /— 164
sections, including uninitialized data, zero out system memory
specified by section
FIG. 3
U.S. Patent
(
Jun. 15,1999
Sheet 4 of 6
create real mode interface
5,913,058
Y’ 108
copy real mode code portion of lOP loader driver into real-mode /— 130
addressable portion of system memory if necessary
¢
132
patch addresses in cache flush real mode code
l
save current states of first processor and interrupt control logic /— 134
which were set by host OS
t
program the local APIC LINTO line as a virtual wire to pass
through 8259 interrupts to give the real-mode BIOS the
136
/_
appearance of a DOS environment
l
program lOAPlC redirection table 0 to physical destination mode
138
with the physical destination as the CPU ID (local APICID) of the r
first processor executing the IOP loader driver
l
program lOAPlC redirection table 0 to virtual wire mode to permit /— ‘I40
the 8259 lNTR line to pass through the IOAPIC
l
disable the real-time clock interrupt to prevent unwanted RTC
[- 142
events during real-mode operation
l
provide a tiled mapping between protected-mode/page enabled
144
code selector and real-mode segment for transition between real- f
mode and protected mode
‘L
program 8259 interrupt controller with DOS lRQ vectors
FIG. 4
146
U.S. Patent
Jun. 15,1999
C
Sheet 6 of6
destroy real mode interface
5,913,058
Y 112
program 8259 interrupt controller with original lRQ vectors
l
restore original address mapping
.
.
.
.
restore interrupt control logic to original state
l,
enable the real-time clock interrupt
FIG. 6
/_ 152
/— 154
5,913,058
1
2
SYSTEM AND METHOD FOR USING A
REAL MODE BIOS INTERFACE TO READ
PHYSICAL DISK SECTORS AFTER THE
OPERATING SYSTEM HAS LOADED AND
BEFORE THE OPERATING SYSTEM
DEVICE DRIVERS HAVE LOADED
fully set forth herein. The referenced patent application
describes a method for dedicating one of the system
processors, such as a Pentium processor in a multiprocessor
system, to perform the functions of an 120 processor. That
is, the dedicated I/O system processor executes the 120
real-time kernel, Which is dissimilar from the host operating
system executing on the remaining system processors. The
dedicated I/O system processor also executes those portions
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to multiprocessor computer
10
the hardWare interface speci?ed for 120 devices using sys
systems, and in particular to dedicated input/output (I/O)
processors in computer systems.
2. Description of the Related Art
Multiprocessor computer systems have become common
place. For example, many personal computers Which com
tem memory rather than actual hardWare FIFOs. Thus, in at
least one example, it is desirable to execute a softWare
program dissimilar from the host operating system on one of
15
prise a plurality of Intel Pentium® or Pentium-class proces
sors are available in the marketplace. These multiprocessor
systems are largely employed in netWork server environ
I/O operations must be performed in netWork server sys
tems. The U0 operations involve the transfer of data
betWeen I/O devices and system memory. An operating
system, such as WindoWs NT or UNIX, poses some prob
lems. Typically, the host operating system is loaded from a
non-volatile storage device, such as a disk drive. The oper
25
processors programs the I/O devices to perform the I/O
operations. Furthermore, the device drivers of the operating
system executing on the system processors perform other
I/O-related functions such as servicing interrupts generated
by the I/O devices.
In many cases, the I/O processing performed by the
Output System (BIOS) disk service calls, e.g., INT13H
processors is to serve as a dedicated I/O processor in the
35
the Intelligent I/O (IZO) architecture. The 120 standard is
described in the 120 Architecture Speci?cation, Draft Revi
SUMMARY OF THE INVENTION
45
portions of device drivers from the system processors to the
dedicated I/O processors. According to this architecture, the
portions of the device driver Which remain in the host
The problems outlined above are in large part solved by
the system and method of the present invention for using real
mode BIOS calls to load an executable program for execu
tion on a dedicated I/O processor before device drivers
Which communicate With the I/O processor have been
operating system are relatively small, portable and easily
loaded by an operating system. In the preferred embodiment,
the system comprises a plurality of x86 processors coupled
maintained.
The 120 architecture provides a real-time kernel Which
executes on an I/O processor Which controls one or more I/O
devices. Portions of the device drivers for the I/O devices
from the host operating system are adapted and migrated to
execute on the I/O processor in conjunction With the real
time kernel. The architecture speci?es an interface for host
system, programs such as the real-time kernel Which
executes on the dedicated I/O system processor must be
loaded into system memory and executed on the dedicated
I/O system processor prior to the time When the device
driver executing on the host system processors attempts to
access the dedicated I/O system processor. Thus, a system
and method is desired for loading an executable program
from a non-volatile storage device after the host operating
system has been loaded but prior to execution of the host
operating system device drivers.
sion 1.5, March 1997, Which is hereby incorporated by
reference in its entirety. The 120 architecture is independent
of operating system, processor platform, and system I/O bus.
The speci?cation provides a means for migrating large
ating system is loaded from the disk drive by some operating
system independent means, such as using Basic Input/
calls, While in real mode. Device drivers are also loaded and
after sWitching to protected mode, the device drivers access
their associated I/O devices. HoWever, if one of the system
system processors, particularly interrupt servicing and
accessing registers Within the I/O devices across an I/O bus
to Which the I/O devices are coupled, constitute a large
processing bandWidth burden on the system processors.
Hence, a trend toWard dedicated I/O processors to offload
the system processors has appeared. An example of a
contemporary architecture Which employs I/O processors to
offload I/O processing functions from system processors is
the multiple processors in a multiprocessor system.
A pertinent characteristic of x86 processors is that they
are capable of running in mixed modes, namely real mode
and protected mode, as is Well knoWn in the art of program
ming x86 processors. The fact that the system processors
initially run in real mode but eventually are typically
sWitched to run in protected mode by the host operating
ments Which require large amounts of input/output (I/O). For
example, many mass storage I/O operations and/or netWork
system, in particular device drivers, executing on the system
of the device drivers Which are migrated to the I/O proces
sor. The dedicated I/ O system processor essentially emulates
55
to a system memory. One of the x86 processors is designated
as a dedicated I/O processor. The system further comprises
a storage device, such as a disk drive. The storage device
stores an operating system for execution on the remaining
processors. The storage device also stores an executable
program for executing on the dedicated I/O processor, such
operating system device drivers to communicate With the
as a real-time kernel. The storage device also stores a device
I/O device drivers executing on the I/O processors across
and I/O bus to Which the I/O devices are coupled.
One approach to a dedicated I/O processor architecture
driver Which is part of the operating system and Which is
operable to execute on the remaining processors and to
communicate With the real-time kernel executing on the I/O
processor to perform I/O operations on an I/O device
has been disclosed in US. patent application Ser. No.
09/152,997 entitled Method and System for Implementing
Intelligent Distribution Input/Output Processing in a Multi
Processor Computer System (P-1359) Which Was ?led on
Sep. 14, 1998, Whose inventor is Thomas J. Bonola, Which
is assigned to Compaq Computer Corporation, and Which is
hereby incorporated by reference in its entirety as though
comprised in the system.
The storage device also stores a loader program, prefer
ably a device driver, Which is loaded by the operating system
65
executing on a ?rst of the remaining processors early in the
process of booting the operating system. Preferably, the
loader program is loaded as the ?rst device driver. The
5,913,058
3
4
loader program executing on the ?rst processor creates a real
mode interface in order to sWitch the ?rst processor to real
the ?rst processor from protected mode into real mode,
reading the program from the storage device into the system
memory While the ?rst processor is in real mode, and
sWitching the ?rst processor back from real mode into
protected mode after the reading the program.
mode. The loader program includes real mode code Which
executes BIOS INT13 disk requests to read sectors of the
real-time kernel from the storage device. Once the ?rst
processor is sWitched to real mode, the real mode code of the
loader program reads the real-time kernel from the storage
device into system memory using BIOS INT13 calls.
After the loader program loads the real-time kernel into
system memory, the loader program causes the I/O processor
to execute the real-time kernel. Once the real-time kernel is
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the invention Will
become apparent upon reading the folloWing detailed
description and upon reference to the accompanying draW
ings in Which:
ready to receive communications from the host operating
FIG. 1 is a block diagram of a multiprocessor computer
system, the loader program returns control back to the host
system according to the preferred embodiment of the present
operating system. The operating system loads the device
driver Which communicates With the real-time kernel
executing on the I/O processor to perform I/O operations on
the I/O device. Thus, the loader program enables the real
time kernel to be loaded into system memory and executed
on the I/O processor prior to the host operating system
loading the device driver Which communicates With the
real-time kernel executing on the I/O processor.
The loader program performs various steps to enable to
the real-time kernel to be loaded via real mode INT13 calls.
invention;
15
real mode, issuing INT13 calls, and sWitching back to
protected mode;
The loader must allocate a chunk of real mode addressable
(i.e. beloW 1 MB) system memory in order to execute real
25
mode code. Aportion of the real mode code executes on the
?rst processor to issue INT13 calls. A portion of the real
mode code executes on the I/O processor When the I/O
FIG. 5 is a block diagram illustrating in more detail the
FIG. 6 is a ?oWchart illustrating in more detail the step of
destroying the real mode interface of FIG. 2.
While the invention is susceptible to various modi?ca
tions and alternative forms, speci?c embodiments thereof
buffer by the BIOS INT13 real mode code to read in sectors
protected mode state of the ?rst processor Which Was set by
the host operating system so that the protected mode state
may be restored When the ?rst processor is sWitched back to
real mode after the INT13 reads are performed. In particular,
the protected mode memory mapping information, e.g.,
segment registers and segment descriptor tables, must be
saved since they Will be altered prior to sWitching to real
mode. Creating the real mode interface also comprises
saving the state of interrupt control logic comprised in the
system. In one embodiment, the interrupt control logic
comprises local interrupt controllers in each of the
processors, a multiprocessor-capable I/O interrupt
controller, and traditional PC-architecture 8259 peripheral
interrupt controllers.
are shoWn by Way of example in the draWings and Will
herein be described in detail. It should be understood,
35
modi?cations, equivalents and alternatives falling Within the
spirit and scope of the present invention as de?ned by the
appended claims.
DETAILED DESCRIPTION OF THE
INVENTION
45
the I/O processor 12d and processors 12a, 12b and 12c Will
be referred to as host processors 12a—c. In the preferred
embodiment, the processors 12a—12a' are x86 processors
such as Pentium processors. In one embodiment, the host
55
since X86 processors compute physical addresses differently
in real mode and protected mode.
Broadly speaking, the computer system of the present
method comprises executing a portion of an operating
system in protected mode on the ?rst processor, sWitching
Referring to FIG. 1, a block diagram of a multiprocessor
computer system 10 is shoWn. The shoWn 10 comprises a
plurality of system processors 12a—12a' coupled to a pro
cessor bus 14. Processor 12d operates as a dedicated I/O
processor. Processors 12a, 12b and 12c execute a host
operating system, such as WindoWs NT or UNIX. For
simplicity and clarity, processor 12d Will be referred to as
control logic to simulate a DOS environment. The loader
invention comprises a plurality of processors, a system
memory, and a storage device having a softWare program
stored thereon, Wherein a ?rst of the processors may operate
in both real mode and protected mode and a second of the
processors may operate in real mode. The invention com
prises a method for loading the program into the system
memory for execution on the second processor, Wherein, the
hoWever, that the draWings and detailed description thereto
are not intended to limit the invention to the particular form
disclosed, but on the contrary, the intention is to cover all
After saving the states of the ?rst processor and interrupt
control logic, the loader program programs the interrupt
program also provides a “tiled mapping” of memory
addresses such that the transition may be made from real
mode to protected mode and vice versa. This is necessary
FIG. 4 is a ?oWchart illustrating in more detail the step of
creating the real mode interface of FIG. 2;
interrupt control logic of the system of FIG. 1;
processor comes out of reset and transfers control to the
real-time kernel to execute on the I/O processor. The real
mode addressable chunk of memory is also used as a sector
from the storage device.
Creating the real mode interface comprises saving the
FIG. 2 is a ?oWchart illustrating steps performed to load
the real-time kernel of FIG. 1 from the storage device of
FIG. 1 into the system memory of FIG. 1 for execution on
the I/O processor of FIG. 1;
FIG. 3 is a ?oWchart illustrating steps performed to load
the real-time kernel of FIG. 1 from the storage device of
FIG. 1 into the system memory of FIG. 1 by sWitching into
processors 12a—c operate as symmetric multiprocessors. The
system 10 further includes one or more I/O deices 24,
preferably coupled to an I/O bus 20. The I/O devices 24 are
controlled by the I/O processor 12d.
The processors 12a—d are also coupled to a system
memory 16, preferably via chipset logic 18, Which includes
a memory controller. The system memory 16 is accessible
by each of the processors 12a—d. In one embodiment, the
chipset logic 18 further includes an I/O bus bridge for
65
coupling the processor bus 14 to the I/O bus 20. In one
embodiment, the I/O bus 20 is a PCI bus.
The system 10 further includes a non-volatile storage
device 22, such as a disk drive, preferably coupled to the I/O
5,913,058
5
6
bus 20. Stored on the storage device 22 is the host operating
system 26. The host operating system 26 is loaded from the
storage device 22 into the system memory 16 at boot time
and executed on the host processors 12a—c. The storage
device 22 further includes device drivers 28. The device
entry point Which replaces a previous softWare interrupt 13
entry in an interrupt vector table of the ?rst processor 12a.
Consequently, the option ROM entry point is vectored to in
response to the execution of an INT13 instruction by the ?rst
processor 12a. More about the operation of the BIOS 34, and
in particular INT13 disk services, Will be described beloW.
drivers 28 also execute on the host processors 12a—c. The
device drivers 28 communicate With the I/O processor 12d
to request I/O operations of the I/O devices 24.
The system 10 further comprises interrupt control logic 36
coupled to the processors 12a—d. Preferably, the interrupt
control logic 36 comprises an I/O Advanced Programmable
Interrupt Controller (IOAPIC), master and slave 8259A
Peripheral Interrupt Controllers (PICs), and a local
Advanced Programmable Interrupt Controller (APIC) asso
The storage device 22 further includes an real-time oper
ating system 30, or kernel, Which is loaded from the storage
device 22 into the system memory 16 for execution on the
I/O processor 12d. Preferably, the device drivers 28 and the
real-time kernel 30 executing on the I/O processor 12d
communicate via a shared region of the system memory 16.
The present invention advantageously provides a method for
loading the real-time kernel 30 from the storage device 22
into memory 16 after the host operating system 26 has been
loaded into memory 16 and before the device drivers 28
have been loaded into memory 16. In particular, the real
ciated With each of the processors 12a—d. In one
embodiment, the local APICs are comprised Within the
15
sources in the system 10, such as the I/O device 24, and
controls the routing of the interrupt request signals 38 to the
processors 12a—d. Preferably, the interrupt control logic 36
comprises interrupt control logic external to the processors
time kernel 30 is loaded and executed on the I/O processor
12d prior to the device drivers 28 making requests of the I/O
12a—d as Well as interrupt control logic integrated in each of
processor 12d. The real-time kernel 30 is loaded by a loader
program 32, preferably stored on the storage device 22. In
the preferred embodiment, the loader 32 is a device driver
Which is loaded by the operating system before the device
the processors 12a—d, as Will be described in more detail
With respect to FIG. 5.
Referring noW to FIG. 2, a ?oWchart is shoWn illustrating
25
drivers 28 Which communicate With the I/O processor 12d.
In one embodiment, the storage device 22 is one of the I/O
devices 24 Which may be controlled by the I/O processor
12d. In one embodiment, the real-time kernel 30 comprises
an 120 real-time kernel compiled for an X86 processor, i.e.,
compiled to execute on the I/O processor 12d and migrated
portions of device drivers for the I/O device 24.
Although an embodiment is described in Which the real
time kernel 30 is executed on the I/O processor 12d, the
present invention is advantageous for loading any softWare
processors 12a—d. The interrupt control logic 36 logic
receives interrupt request signals 38 from various interrupt
steps performed to load the real-time kernel 30 from the
storage device 22 into the system memory 16 for execution
on the I/O processor 12d. For clarity and simplicity a ?rst of
the host processors 12a—c Will be designated in the descrip
tion folloWing as the “?rst processor 12a”, indicating the
processor Which loads the real-time kernel 30 into the
system memory 16. It is noted that preferably, any of the
host processors 12a—c may be used to load the real-time
kernel 30.
35
As described earlier, in the preferred embodiment, the
program onto the I/O processor 12d Which must be loaded
processors 12a—d are x86 processors. Preferably, the x86
after the operating system and before device drivers. In other
processors are of the 80386 class of x86 processor or
embodiments, hardWare devices other than an 120 device are
subsequent processors of the x86 architecture processors,
such as the 80486 class, Pentium class and Pentium Pro
class. In particular, the processors 12a—d are capable of
operating in either of at least tWo modes: real mode and
emulated. In particular, the present system and method is
useful for emulating neW I/O device hardWare prior to the
development of the hardWare so that device driver softWare
may be developed for the neW hardWare before the neW
protected mode. Real mode and protected mode operation of
hardWare is available. Examples of other I/O device hard
x86 processors is Well knoWn in the art of programming x86
processors. HoWever, a brief discussion of pertinent aspects
Ware include video controllers and netWork interface con
trollers.
The system 10 further includes a Basic Input/Output
45
of real and protected mode operation Will be given here.
One pertinent limitation of an x86 processor operating in
System (BIOS) 34 comprised in a non-volatile memory,
real mode is the processor is only capable of addressing 1
such as an EPROM or FLASH memory. In one embodiment,
MB of physical memory. Thus, in a system such as system
10, if the system memory 16 includes more than 1 MB of
memory, the processor cannot address the memory above 1
the BIOS 34 is coupled to the host bus 14. In one
embodiment, the BIOS 34 is coupled to the I/O bus 20 or an
ancillary I/O bus, such as an Industry Standard Architecture
MB When operating in real mode. Another pertinent limita
tion of x86 processor-based personal computers is that the
BIOS routines, in particular the softWare interrupt 13H disk
(ISA) bus, bridged to the I/O bus 20. BIOS 34 programs are
Well knoWn in the art of IBM®-compatible personal com
puters.
In particular, the BIOS 34 includes disk services acces
sible via a disk services entry point via real mode softWare
interrupt 13H (commonly referred to as INT13), as is also
Well knoWn in the art of personal computers. The BIOS 34
disk services routines are operable to read and Write speci
?ed sectors of data from a speci?ed storage device, such as
55
limited to real mode execution, they advantageously provide
an operating system independent means of performing disk
I/O. That is, the INT13 disk services provide an “operating
system device driver-less” means of performing disk I/O.
Conversely, in protected mode, an x86 processor is
capable of addressing 4 GB of physical memory. In addition,
many operating systems, such as WindoWs NT, UNIX and
Novell NetWare®, operate in protected mode in order to
storage device 22, While the processor executing the BIOS
program is in real mode. In one embodiment, the BIOS 34
disk services routines Which communicate With the storage
device 22 are comprised in a non-volatile memory com
prised in the storage device 22. Such a BIOS on a peripheral
device is commonly referred to as an “option ROM.” For a
disk storage device, the option ROM includes an INT13
service routines, are typically Written to execute in real
mode. HoWever, although the INT13 disk services are
65
take advantage of the memory protection capabilities offered
by x86 processors in protected mode. Another difference
betWeen real and protected mode operation of x86 proces
sors is the manner in Which segment registers are used to
5,913,058
7
8
perform segmentation of memory. As is Well known in the
art of programming X86 processors, in real mode the seg
ment registers are used to specify memory segments,
Whereas in protected mode the segment registers are used to
real mode code portions of itself into this reserved chunk of
memory. The real mode code comprises a portion for
execution by the ?rst processor 12a in real mode and a
portion for execution by the I/O processor 12d in real mode.
Furthermore, a portion of the reserved memory chunk in real
specify descriptors of memory segments.
Description is made below of one embodiment of the
mode addressable memory is used as a sector buffer for the
present invention executing in the WindoWs NT operating
BIOS INT13 routine to read sectors into from the storage
device 22.
system and is operable to load an image from a storage
device having a DOS FAT ?le system. HoWever, it Will be
obvious to one skilled in the art of device driver develop
ment in light of the present disclosure to adapt the method
disclosed to other operating systems and other ?le systems.
During the boot process of the host operating system 26,
the ?rst processor 12a sWitches to protected mode, in step
100. The ?rst processor 12a then loads the host operating
system 26 from the storage device 22 into system memory
16, in step 102 and transfers control to the host operating
system 26. In one embodiment, the host operating system 26
is loaded into system memory 16 and then the ?rst processor
12a is sWitched into protected mode.
In one embodiment, only a portion of the host operating
system 26 is loaded into memory 16. Preferably, the kernel
portion of the host operating system 26 is loaded into
memory 16. The kernel portion is intended to distinguish the
device driver portions of the host operating system 26 from
the remainder of the host operating system 26. That is,
preferably the kernel portion does not include the device
drivers of the host operating system 26. Preferably, the ?rst
processor 12a sWitches into protected mode prior to loading
the host operating system 26 kernel into system memory 16
so that portions of the host operating system 26 may be
loaded into system memory 16 ranges above the real mode
memory addressability range, i.e., above 1 MB. HoWever, in
one embodiment, When control is transferred to the host
operating system 26, the host operating system 26 sWitches
In step 108, The loader program 32, operating on the ?rst
10
processor 12a, creates a real mode interface to enable itself
to load the real-time kernel 30, using BIOS 34 INT13 calls,
into system memory 16 for execution on the I/O processor
15
12d. Step 108 Will be described in detail With regard to FIG.
4 beloW. Among other things, creating a real mode interface
includes saving the state of the ?rst processor 12a and
interrupt control logic 36; programming the interrupt control
logic 36 for real mode operation; disabling the real-time
system clock interrupt; and, providing a memory mapping
betWeen protected mode and real mode.
In step 110, the loader program 32 loads the real-time
kernel 30 into system memory 16 by sWitching to real mode,
issuing BIOS 34 INT13 calls, and sWitching back to pro
25
tected mode. Step 110 Will be described noW in detail With
reference to FIG. 3.
Referring noW to FIG. 3, a How chart is shoWn illustrating
steps performed to load the real-time kernel 30 from the
storage device 22 into the system memory 16 by sWitching
into real mode, issuing INT13 calls, and sWitching back to
protected mode. Preferably, the real-time kernel 30 is com
prised Within an executable image ?le, also referred to as an
image ?le, in a ?le system on the storage device 22. In step
160, the ?rst processor 12a opens the image ?le, i.e., the ?le
including the real-time kernel 30.
35
Preferably, opening the real-time kernel 30 ?le comprises
reading the master boot record of the storage device 22 and
the ?rst processor 12a to protected mode.
Next, the ?rst processor 12a loads the loader program 32
scanning the partition table looking for a bootable partition
from the storage device into system memory 16, in step 104,
Opening the real-time kernel 30 ?le further comprises
determining storage device 22 parameters, and ?le system
of the desired ?le system type, such as a DOS FAT partition.
and transfers control to the loader program 32. In one
data structure information, such as FAT root directory infor
mation and ?le data area information. Opening the real-time
embodiment, the loader program 32 is a device driver, such
as a WindoWs NT device driver. Transferring control com
prises executing an initialiZation routine of the loader pro
gram 32 driver. In one embodiment, the host operating
system 26 kernel is con?gured to load the loader program 32
as the ?rst device driver, i.e., prior to any other device
kernel 30 ?le further comprises searching the ?le system
45
drivers in the system. Preferably, during installation of the
loader program 32 device driver, a WindoWs Registry is
updated to request the loader program 32 driver to be loaded
as the ?rst device driver by the host operating system 26.
Loading the loader program 32 driver ?rst minimiZes the
possibility that all of the loWer 1 MB of memory is con
sumed before the loader program 32 driver initialiZation
routine is executed. In another embodiment, the loader
program 32 and the device drivers are comprised Within the
host operating system 26 and are loaded along With the host
operating system 26 in step 102. HoWever, in this
embodiment, the initialiZation routine of the loader program
32 device driver is executed prior to execution of the
initialiZation routines of any of the other device drivers in
the host operating system 26.
directory to determine the location in the ?le system of the
real-time kernel 30 ?le.
In order to perform the reads necessary to open the
real-time kernel 30 ?le, the ?rst processor 12a sWitches to
real mode, issues an INT13 call, and sWitches back to
protected mode. Preferably, the real mode addressable sector
buffer is passed as the destination address parameter to the
INT13 calls for reading the required sectors from the storage
device 22 such as the master boot record and ?le system data
structure information. Preferably, the ?rst processor 12a
copies the data read from the storage device 22 into the real
55
mode addressable sector buffer to the desired location in
system memory 16, Which may be outside of the real mode
addressable range. Preferably, the ?rst processor 12a com
putes INT13 parameters, such as sector counts and starting
head, cylinder and sector values from logical sector infor
mation of the ?le data area information and from the storage
device 22 parameters previously obtained. The code Which
executes the INT13 calls comprises portions of the loader
The loader program 32, operating on the ?rst processor
12a, “locks doWn”, i.e., allocates or reserves, a chunk of
program 32 Which execute in real mode on the ?rst processor
system memory 16 in the loWer 1 MB, in step 106. That is,
12a. This code is copied to the chunk of system memory 16
the loader program 32 reserves a chunk of system memory 65 Which Was reserved in step 106.
16 Which is addressable by the processors 12a—d in real
mode. In a subsequent step, the loader program 32 Will copy
Preferably, the executable image ?le comprises a header
portion Which speci?es various sections of the executable
5,913,058
9
10
image comprised therein, such as code sections, initialized
receiving requests from the host processors 12a—c to per
form I/O operations on the I/O device 24.
After spaWning the real-time kernel 30 on the I/O pro
cessor 12d and being noti?ed by the real-time kernel 30 that
the real-time kernel 30 has completed its initialiZation, the
loader program 32 returns control back to the host operating
system 26. The host operating system 26 loads other device
drivers into system memory 16. In particular, the host
operating system 26 loads the device driver 28 Which
communicates With the real-time kernel 30 executing on the
I/O processor 12d to effectuate I/O operations on the I/O
device 24, in step 116. Thus, the ?oWchart of FIG. 2
illustrates a method for using real mode BIOS INT13 calls
data sections and uninitialized data sections. Executable
image ?le formats are Well knoWn in the art of computer
programming. The ?rst processor 12a reads the image ?le
header, in step 162.
In step 164, the ?rst processor 12a scans the header
looking at the description of each section to determine the
type of section. For each section Which is a code section or
an initialiZed data section, the ?rst processor 12a loads the
section from the image ?le on the storage device 22 into
10
system memory 16 using address information speci?ed in
the section descriptions in the header. Loading the sections
comprises sWitching the ?rst processor 12a to real mode,
issuing an INT13 call, and sWitching the ?rst processor 12a
back to protected mode. The code Which executes the INT13
15
calls comprises portions of the loader program 32 Which
communicate With the executable image executing on the
execute in real mode on the ?rst processor 12a. This code is
copied to the chunk of system memory 16 Which Was
reserved in step 106.
Preferably, the real mode addressable sector buffer is
passed as the destination address parameter to the INT13
call for reading the sectors from the storage device 22 Which
include the executable image sections of the real-time kernel
30 ?le. Preferably, the ?rst processor 12a copies the data
read from the storage device 22 into the real mode addres
to load an executable image into system memory for execu
tion on a second processor after the operating system has
loaded and before device drivers have been loaded Which
second processor.
Referring noW to FIG. 4, a ?oWchart illustrating in more
detail step 108 of FIG. 2, creating the real mode interface,
is shoWn. The portions of the loader program 32 Which
execute in real mode on the ?rst processor 12a and the I/O
processor 12d and the sector buffer must reside in a real
25
sable sector buffer to the desired location in system memory
16, Which may be outside of the real mode addressable
mode addressable portion of system memory 16. Therefore,
if the host operating system 26 loaded the real mode portion
of the loader program 32 into a region of system memory 16
Which is not addressable in real mode, the loader program 32
allocates a chunk of real mode addressable system memory
16, and copies the real mode code to the allocated chunk of
range. Preferably, the ?rst processor 12a computes INT13
parameters, such as sector counts and starting head, cylinder
and sector values from logical sector information of the ?le
system memory 16, in step 130.
data area information and from the storage device 22 param
It is necessary for the ?rst processor 12a to cause a reload
eters previously obtained. For each other section, including
uninitialiZed data sections, the ?rst processor 12aclears, i.e.,
?lls With Zeros, the system memory 16 locations speci?ed in
the header section descriptions. Thus, multiple sWitches
betWeen real and protected mode are performed by the
of the Code Segment (CS) register and a ?ush of a pre-fetch
instruction queue comprised in the ?rst processor 12a When
sWitching betWeen real mode and protected mode or vice
versa. Therefore, the real mode code portion of the loader
program 32 comprises instructions Which perform an inter
loader program 32 to load the real-time kernel 30.
Thus, the loader program 32 loads the real-time kernel 30
sWitch the ?rst processor 12a betWeen real mode and
segment jump immediately folloWing the instructions Which
using operating system independent INT13 calls. This is
advantageous in that the real-time kernel 30 may be
executed on the I/O processor 12d prior to the host operating
system 26 loading a device driver 28 Which Will try to
communicate With the real-time kernel 30 executing on the
I/O processor 12d to control the I/O device 24.
Referring again to FIG. 2, after loading the real-time
protected mode. These instructions must be patched With the
appropriate destination address of the jump instruction. The
loader program 32 patches the addresses of the real mode
code portions Which perform the ?ushing, in step 132.
The loader program 32 saves the protected mode state of
45
the ?rst processor 12a and of the interrupt control logic 36
Which Were set by the host operating system 26, in step 134.
kernel 30 into system memory 16, the ?rst processor 12a
In particular, the loader program 32 saves the state of the x86
destroys the real mode interface, in step 112. Step 112 Will
global descriptor table (GDT), since the loader program 32
be described in detail With regard to FIG. 6 beloW.
Once the real-time kernel 30 has been loaded into system
memory 16, the ?rst processor 12a spaWns off the real-time
kernel 30 onto the I/O processor 12d, in step 114. That is, the
?rst processor 12a causes the I/O processor 12d to begin
Will modify the GDT in a subsequent step.
Referring noW to FIG. 5, a block diagram illustrating in
more detail the interrupt control logic 36 in the preferred
embodiment of the system 10 is shoWn. The interrupt control
logic 36 comprises a local Advanced Programmable Inter
executing the real-time kernel 30. Preferably, spaWning off
the real-time kernel 30 onto the I/ O processor 12d comprises
the ?rst processor 12a causing the I/O processor 12d to
rupt Controller (APIC) 40a comprised Within processor 12a
55
(not shoWn). For simplicity and clarity, the local APICs
execute a startup program When the I/O processor 12d
comes out of reset. The startup program comprises portions
of the loader program 32 Which execute in real mode on the
I/O processor 12d after the I/O processor 12d comes out of
comprised in the processors 12a—d are referred to as local
APICs 40 collectively. It is noted that the local APICs need
not necessarily be comprised Within the processors 12a—d,
reset. The startup program is copied to the chunk of system
but rather may be external and coupled to the processors
12a—d.
memory 16 Which Was reserved in step 106.
The startup program, executing on the I/O processor 12d
in real mode after coming out of reset, initialiZes the I/O
processor 12d environment, sWitches the I/O processor 12d
to protected mode, and transfers execution to the real-time
kernel 30. Thus, the I/O processor 12d is noW capable of
and a local APIC 40d comprised Within processor 12d.
Preferably, processors 12b and 12c also include local APICs
The interrupt control logic 36 further comprises an I/O
Advanced Programmable Interrupt Controller (IOAPIC) 42
65
coupled to the local APICs 40. The interrupt control logic 36
further comprises a master 8259A PIC 44a and a slave
8259A PIC 44b, referred to collectively as the 8259A 44.
5,913,058
11
12
The IOAPIC 42 and the 8259A 44 receive interrupt signals
mapping and restores the mapping to the mapping set by the
host operating system 26. The loader program 32 restores
the interrupt control logic 36 to its original state, i.e., the host
operating system 26 programmed state, in step 154. Restor
ing the interrupt control logic 36 state includes restoring the
38 from the interrupt sources in the system 10, such as the
8254 timer real-time clock (RTC) interrupt, and control the
routing of the interrupt sources to the processors 12a—d. The
various portions of the interrupt control logic 36 are
described in detail in the Intel Multiprocessor Speci?cation
Version 1.4, August 1996, Which is hereby incorporated by
state of the local APICs 40, the state of the IOAPIC 42, and
the state of the 8259A 44. The loader program 32 enables the
reference in its entirety as though fully set forth herein.
RTC, in step 156.
Programming of the interrupt control logic 36 Will be
APIC LINTO line 50 as a virtual Wire to pass through
Further modi?cations and alternative embodiments of
various aspects of the invention Will be apparent to those
skilled in the art in vieW of this description. Accordingly, this
description is to be construed as illustrative only and is for
the purpose of teaching those skilled in the art the general
manner of carrying out the invention. It is to be understood
that the forms of the invention shoWn and described herein
are to be taken as the presently preferred embodiments.
Elements and materials may be substituted for those illus
trated and described herein, parts and processes may be
reversed, and certain features of the invention may be
interrupts from the 8259A 44, in step 136. Programming the
utiliZed independently, all as Would be apparent to one
local APIC 40a in this manner gives the BIOS 34 the
appearance of a DOS environment. The loader program 32
programs redirection table 0 of the IOAPIC 42 to physical
destination mode and programs the physical destination to
be the ID of the local APIC 40a of the ?rst processor 12a,
in step 138. The loader program 32 programs redirection
table 0 of the IOAPIC 42 to virtual Wire mode such that the
INTR line 46 from the master 8259A 44a passes through the
skilled in the art after having the bene?t of this description
of the invention. Changes may be made in the elements
described herein Without departing from the spirit and scope
of the invention as described in the folloWing claims.
What is claimed is:
1. In a computer system having a plurality of processors
connected together by a processor bus, at least one of said
processors being capable of executing instructions in a
protected mode and a real mode, a system memory that is
accessible by at least tWo of said plurality of processors, a
storage device that stores information that is accessible by at
described in more detail With reference to the ?oWchart of
FIG. 4 beloW.
Referring again to FIG. 4, the loader program 32 saves the
state of the interrupt control logic 36 Which Was set by the
host operating system 26, in step 134. Preferably, saving the
state of the interrupt control logic 36 comprises saving the
15
state of the local APICs 40, the state of the IOAPIC 42, and
the state of the 8259A 44.
The loader program 32 programs the ?rst processor local
25
IOAPIC 42, in step 140. Steps 136, 138, 140 and/or 146
(beloW) serve to program the interrupt control logic 36 to a
real mode emulation state so that the real mode BIOS 34
INT13 code executes properly. The loader program 32
least one of said plurality of processors, a method for
loading executable instructions into said system memory
using a ?rst of said plurality of processors for execution by
disables the real-time clock (RTC) interrupt 48 to prevent
undesirable RTC events during real mode operation, in step
142.
As is Well knoWn in X86 programming, in real mode, the
35
executing instructions With said ?rst of said plurality of
processors in said protected mode sWitching said ?rst
of said plurality of processors into said real mode;
physical address generated by the processor When fetching
an instruction is computed as the sum of an offset value and
the Code Segment (CS) register shifted left 4 bits. HoWever,
in protected mode, the value of the CS register is used as a
segment selector for indexing into the GDT to select a
segment descriptor. The segment descriptor contains a base
address Which is added to the offset to produce a linear
address. The linear address is then translated into a physical
address by a paging unit, if paging is enabled.
45
may be referred to as a “tiled” mapping. That is, a 1:1
address mapping is provided such that When the ?rst pro
55
mode sWitch. Preferably, the loader program 32 provides
this mapping for host operating systems 26 Where paging is
executing instructions in said real mode to sWitch said
?rst of said plurality of processors back into said
protected mode after loading said at least a portion of
said information into said system memory;
accessing said at least a portion of said information in said
system memory With a second of said plurality of
processors after said at least a portion of said informa
tion is loaded into said system memory by said ?rst of
said plurality of processors; and
executing instructions corresponding to said portion of
enabled. The loader program 32 programs the master 825 9A
said information With said second of said plurality of
processors after accessing said at least a portion of said
information in said system memory With said second of
44a and slave 8259A 44b to support DOS interrupt request
(IRQ) vectors, in step 146.
said plurality of processors.
2. The method of claim 1, Wherein said reading comprises
Referring noW to FIG. 6, a ?oWchart illustrating in more
detail step 112 of FIG. 2, destroying the real mode interface,
issuing one or more Basic Input/Output System (BIOS) disk
is shoWn. The loader program 32 programs the master
8259A 44a and slave 8259A 44b to the original IRQ vectors
set up by the host operating system 26, in step 150. The
loader program 32 restores the original address mapping, in
step 152. That is, the loader program 32 destroys the tiled
reading at least a portion of said information from said
storage device With said ?rst of said plurality of pro
cessors after sWitching into said real mode;
loading said at least a portion of said information into said
system memory With said ?rst of said plurality of
processors after reading said at least a portion of said
information from said storage device;
The loader program 32 provides a mapping betWeen the
physical addresses generated by the ?rst processor 12a in
real mode and in protected mode, in step 144. This mapping
cessor 12a is sWitched betWeen real and protected mode the
next instruction fetched after the instruction Which effectu
ated the mode sWitch is the instruction in the next physical
memory location after the instruction Which effectuated the
a second of said plurality of processors, said method com
prising:
65
service requests.
3. The method of claim 1, further comprising:
reading a device driver from said storage device into said
system memory after executing said instructions cor
5,913,058
14
13
responding to said portion of said information With said
second of said plurality of processors, Wherein said
device driver is operable to issue a request to said
instructions executed With said second of said plurality
of processors to control an input/output device com
prised in said computer system.
4. The method of claim 1, further comprising:
reserving a portion of said system memory Within a range
of addresses of said system memory addressable by
said ?rst of said plurality of processors and a second of
said plurality of processors in said real mode prior to
said reading said at least a portion of said information
from said storage device.
5. The method of claim 1, further comprising:
reading a second portion of said information from said
storage device into said system memory prior to said
reading said at least a portion of said information from
10
at least one of said plurality of processors, said computer
system comprising:
a ?rst of said plurality of processors, said ?rst of said
15
tion of said information on said ?rst of said plurality of
into said protected mode; and
25
after said at least a portion of said information is loaded
?rst of said plurality of processors, and said executing
into said system memory by said ?rst of said plurality
of processors, said second of said plurality of proces
instructions in said real mode to sWitch said ?rst of said
plurality of processors back into said protected mode.
6. The method of claim 1, Wherein said second portion
sors then executing instructions corresponding to said
comprises a device driver.
7. The method of claim 1, further comprising:
35
computer system to a real mode emulation state.
8. The method of claim 1, further comprising:
programming a destination of interrupt control logic com
prised in said computer system to said ?rst of said
plurality of processors.
9. The method of claim 1, further comprising:
providing a mapping of said system memory for sWitch
ing said ?rst of said plurality of processors betWeen
said protected mode and said real mode.
10. The method of claim 1, further comprising:
disabling a real-time clock interrupt comprised in said
computer system to said ?rst of said plurality of pro
cessors prior to said executing said instructions With
said ?rst of said plurality of processors in said protected
mode sWitching said ?rst of said plurality of processors
17. The system of claim 15, further comprising:
an input/output device;
45
into said real mode.
55
information into said system memory, and execute
instructions corresponding to said second portion of
said information;
With said ?rst of said plurality of processors in said
protected mode sWitching said ?rst of said plurality of
processors into said real mode.
12. The method of claim 11, Wherein said saving said state
comprises saving a state of said ?rst of said plurality of
Wherein said second portion of said information is oper
able to sWitch said ?rst of said plurality of processors
into said real mode, read said at least a portion of said
information from said storage device and load said at
least a portion of said information into said system
memory, and sWitch said ?rst of said plurality of
processors back into said protected mode.
processors.
13. The method of claim 11, Wherein said saving said state
restoring said state of said computer system after said
reading said at least a portion of said information from
Wherein said ?rst of said plurality of processors is oper
able to read a device driver from said storage device,
load said device driver into said system memory, and
execute said device driver;
Wherein said device driver is operable to issue a request
to said instructions corresponding to said portion of
said information executing on said second of said
plurality of processors to control said input/output
device.
18. The system of claim 15,
Wherein said ?rst of said plurality of processors is oper
able to read a second portion of said information from
said storage device, load said second portion of said
saving a state of said computer system While in said
comprises saving a state of interrupt control logic comprised
in said computer system.
14. The method of claim 11, further comprising:
portion of said information.
16. The system of claim 15, further comprising:
a Basic Input/Output System (BIOS), Wherein said ?rst of
said plurality of processors is operable to execute said
BIOS to read said at least a portion of said information
from said storage device and load said at least a portion
of said information into said system memory.
11. The method of claim 1, further comprising:
protected mode prior to said executing said instructions
a second of said plurality of processors, said second of
said plurality of processors accessing said at least a
portion of said information from said system memory
of said information into said system memory With said
programming interrupt control logic comprised in said
plurality of processors executing instructions in said
protected mode sWitching said ?rst of said plurality of
processors into said real mode, then after sWitching into
real mode said ?rst of said plurality of processors
reading at least a portion of said information from said
storage device and loading said at least a portion of said
information into said system memory, then after load
ing said at least a portion of said information into said
system memory said ?rst of said plurality of processors
executing instructions in said real mode to sWitch back
said storage device; and
executing instructions corresponding to said second por
processors after said reading said second portion;
Wherein said second portion of said information is oper
able to perform said executing instructions With said
?rst of said plurality of processors in said protected
mode sWitching said ?rst of said plurality of processors
into said real mode, said loading said at least a portion
said storage device With said ?rst of said plurality of
processors and prior to said executing said instructions
in said real mode to sWitch said ?rst of said plurality of
processors back into said protected mode.
15. A computer system having a plurality of processors
connected together by a processor bus, at least one of said
processors being capable of executing instructions in a
protected mode and a real mode, a system memory that is
accessible by at least tWo of said plurality of processors and
a storage device that stores information that is accessible by
65
19. The system of claim 15, further comprising:
interrupt control logic for receiving a plurality of interrupt
requests and controlling forWarding of said plurality of
5,913,058
15
16
interrupt requests to said plurality of processors,
Wherein said ?rst of said plurality of processors is
reserving a portion of said system memory Within a range
operable to program said interrupt control logic to a
said ?rst of said plurality of processors and a second of
said plurality of processors in said real mode prior to
said reading said at least a portion of said information
from said storage device.
24. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
reading a second portion of said information from said
of addresses of said system memory addressable by
real mode emulation state.
20. Acomputer-readable storage medium comprising pro
gram instructions for execution in a computer system com
prising a plurality of processors connected together by a
processor bus, at least one of said processors being capable
of executing instructions in a protected mode and a real
mode, a system memory that is accessible by at least tWo of
said plurality of processors, a storage device that stores
information that is accessible by at least one of said plurality
of processors, Wherein said computer system is operable to
10
said storage device; and
executing instructions corresponding to said second por
load executable instructions into said system memory using
a ?rst of said plurality of processors for execution by a
second of said plurality of processors, Wherein said program
instructions are operable to implement the steps of:
executing instruction With said ?rst of said plurality of
processors in said protected mode sWitching said ?rst
of said plurality of processors into said real mode;
reading at least a portion of said information from said
storage device With said ?rst of said plurality of pro
cessors after sWitching into said real mode;
loading said at least a portion of said information into said
system memory With said ?rst of said plurality of
processors after reading said at least a portion of said
15
of said information into said system memory With said
?rst of said plurality of processors, and said executing
instructions in said real mode to sWitch said ?rst of said
25
computer system to a real mode emulation state.
26. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
programming a destination of interrupt control logic com
prised in said computer system to said ?rst of said
35
said information With said second of said plurality of
processors after accessing said at least a portion of said
information in said system memory With said second of
said plurality of processors.
21. The medium of claim 20, Wherein said reading com
prises issuing one or more Basic Input/Output System
45
22. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
reading a device driver from said storage device into said
system memory after executing said instructions cor
responding to said portion of said information With said
second of said plurality of processors, Wherein said
device driver is operable to issue a request to said
instructions executed With said second of said plurality
23. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
plurality of processors.
27. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
providing a mapping of said system memory for sWitch
ing said ?rst of said plurality of processors betWeen
said protected mode and said real mode.
28. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
disabling a real-time clock interrupt comprised in said
computer system to said ?rst of said plurality of pro
cessors prior to said executing said instructions With
said ?rst of said plurality of processors in said protected
mode sWitching said ?rst of said plurality of processors
into said real mode.
29. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
saving a state of said computer system While in said
protected mode prior to said executing said instructions
With said ?rst of said plurality of processors in said
protected mode sWitching said ?rst of said plurality of
of processors to control an input/output device com
prised in said computer system.
plurality of processors back into said protected mode.
25. The medium of claim 20, Wherein said program
instructions are further operable to implement the step of:
programming interrupt control logic comprised in said
executing instructions corresponding to said portion of
(BIOS) disk service requests.
tion of said information on said ?rst of said plurality of
processors after said reading said second portion;
Wherein said second portion of said information is oper
able to perform said executing instructions With said
?rst of said plurality of processors in said protected
mode sWitching said ?rst of said plurality of processors
into said real mode, said loading said at least a portion
information from said storage device;
executing instructions in said real mode to sWitch said
?rst of said plurality of processors back into said
protected mode after loading said at least a portion of
said information into said system memory;
accessing said at least a portion of said information in said
system memory With a second of said plurality of
processors after said at least a portion of said informa
tion is loaded into said system memory by said ?rst of
said plurality of processors; and
storage device into said system memory prior to said
reading said at least a portion of said information from
55
processors into said real mode.
×

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