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Analog Devices 2 Overview This chapter describes the analog devices supported by PSpice A/D and PSpice. The following information is provided: • device type • format • usage • library location 2-2 Analog Devices Analog Devices This chapter describes the different types of analog devices supported by PSpice and PSpice A/D. These device types include analog primitives, independent and controlled sources, and subcircuit calls. Each device type is described separately, and each description includes the following information as applicable: • A description, and example of, the proper netlist syntax. • The corresponding model types and their description. • The corresponding list of model parameters and their descriptions. • The equivalent circuit diagram and characteristic equations for the model (as required). • References to publications on which the model is based. These analog devices include all of the standard circuit components that normally are not considered part of the two-state (binary) devices that are found in the digital devices. The model library consists of analog models of off-the-shelf parts that can be used directly in circuits that are being developed. Refer to the Library Reference Manual for device models and in which library they can be found. The model library includes models implemented using the .MODEL statement and macromodels implemented as subcircuits with the .SUBCKT statement. This chapter includes a summary table, Table 2-1, which lists all of the analog device primitives supported by the simulator. Each primitive is described in detail in the sections following the table. Device Types 2-3 Device Types PSpice supports many types of analog devices, including sources and general subcircuits. PSpice A/D also supports digital devices. The supported devices are categorized into device types. each of which can have one or more model types. For example, the BJT device type has three model types: NPN, PNP, and LPNP (Lateral PNP). The description of each devices type includes a description of any of the model types it supports. The device declarations in the netlist always begin with the name of the individual device (instance). The first letter of the name determines the device type. What follows the name depends on the device type and its requested characteristics. Table 2-1 summarizes the device types and the general form of their declaration formats. Note The “Device Type” column in the table includes the designator (letter) used in the device modeling. Table 2-1 Analog Device Summary Device Type Letter Declaration Format Page Bipolar Transistor Q Q<name> <collector node> <base node> <emitter node> + 2-54 [substrate node] <model name> [area value] Capacitor C C<name> <+ node> <- node> [model name] <value> + 2-13 [IC=<initial value>] Voltage-Controlled E E<name> <+ node> <- node> <+ controlling node> + <- 2-18 controlling node> <gain> (additional Analog Behavioral Voltage Source Modeling forms: VALUE, TABLE, LAPLACE, and FREQ; additional POLY form) Voltage-Controlled G G<name> <+ node> <- node> <+ controlling node> + <- 2-18 controlling node> <transconductance> (additional Analog Current Source Behavioral Modeling forms: VALUE, TABLE, LAPLACE, and FREQ; additional POLY form) Current-Controlled F 2-20 <gain> (additional POLY form) Current Source Current-Controlled F<name> <+ node> <- node> <controlling V device name> + W Switch 2-4 Analog Devices W <name> <+ switch node> <- switch node> + <controlling V device name> <model name> 2-67 Table 2-1 Analog Device Summary (continued) Device Type Letter Declaration Format Page CurrentControlled Voltage Source H H<name> <+ node> <- node> <controlling V device name> + <transresistance> (additional POLY form) 2-20 Digital Input N N<name> <interface node> <low level node> <high level node> + <model name> <input specification> 2-47 Digital Output O O<name> <interface node> <low level node> <high level node> + <model name> <output specification> 2-50 Digital Primitive* U U<name> <primitive type> ([parameter value]*) + <digital power node> <digital ground node> <node>* + <timing model name> 2-66 Diode D D<name> <anode node> <cathode node> <model name> 2-15 [area value] GaAsFET B B<name> <drain node> <gate node> <source node> + <model name> [area value] 2-6 I<name> <+ node> <- node> [[DC] <value>] + [AC <magnitude value> [phase value]] [transient specification] 2-21 V<name> <+ node> <- node> [[DC] <value>] + [AC <magnitude value> [phase value]] [transient specification] 2-21 L<name> <+ node> <- node> [model name] <value> + [IC=<initial value>] 2-35 Inductor Coupling K K<name> L<inductor name> <L<inductor name>>* + <coupling value> K<name> <L<inductor name>>* <coupling value> + <model name> [size value] 2-31 JFET J<name> <drain node> <gate node> <source node> + <model name> [area value] 2-26 Independent I Current Source & Stimulus Independent V Voltage Source & Stimulus Inductor L J Device Type 2-5 Table 2-1 Analog Device Summary (continued) Device Type Letter Declaration Format Page MOSFET M M<name> <drain node> <gate node> <source node> + <bulk/substrate node> <model name> + [common model parameter]* 2-36 Resistor R R<name> <+ node> <- node> [model name] <value> 2-61 Subcircuit Call X X<name> [node]* <subcircuit name> 2-70 Transmission Line T T<name> <A port + node> <A port - node> + <B port + node> <B port - node> 2-64 Transmission Line Coupling K K<name> T<line name> <T<line name>>* + CM=<coupling capacitance> LM=<coupling inductance> 2-31 S<name> <+ switch node> <- switch node> + <+ controlling node> <- controlling node> <model name> 2-62 VoltageS Controlled Switch *The Digital Primitive and Digital Stimulus device types are generic in form. They have flexible syntax, and can refer to numerous different devices. 2-6 Analog Devices B GaAsFET General Form B<name> <drain node> <gate node> <source node> + <model name> [area value] Examples BIN 100 10 0 GFAST B13 22 14 23 GNOM 2.0 Model Form .MODEL <model name> GASFET [model parameters] As shown in Figure 2-1, the GaAsFET is modeled as an intrinsic FET using an ohmic resistance (RD/area) in series with the drain, another ohmic resistance (RS/area) in series with the source, and another ohmic resistance (RG) in series with the gate. The [area value] is the relative device area and defaults to 1. Figure 2-1 GaAsFET Mode B B GaAsFET 2-7 The LEVEL model parameter selects between different models for the intrinsic GaAsFET: GaAsFET LEVELS LEVEL=1 Definition LEVEL=2 “Raytheon” or “Statz” model (see reference [3]) and is equivalent to the GaAsFET model in SPICE3. “Curtice” model (see reference [1]). Model Parameters Table 2-2 GaAsFET Model Parameters for All Levels Model Parameters Description LEVEL Model index (1 or 2) Units Default 1 -2 .5 -1 2.0 VTO Pinchoff voltage volt ALPHA Saturation voltage parameter volt BETA Transconductance coefficient amp/volt B volt LAMBDA Doping tail extending parameter (LEVEL=2 only) Channel-length modulation volt TAU Conduction current delay time sec 0 RG Gate ohmic resistance ohm 0 RD Drain ohmic resistance ohm 0 RS Source ohmic resistance ohm 0 IS Gate p-n saturation current amp 1E-14 N Gate p-n emission coefficient 1 M Gate p-n grading coefficient 0.5 VBI Gate p-n potential volt 1.0 CGD Zero-bias gate-drain p-n capacitance farad 0 CGS Zero-bias gate-source p-n capacitance farad 0 CDS Drain-source capacitance farad 0 FC Forward-bias depletion capacitance coefficient VTOTC VTO temperature coefficient volt/°C 0 BETATCE BETA exponential temperature coefficient %/°C 0 KF Flicker noise coefficient 0 AF Flicker noise exponent 1 2 0.1 -1 0.3 -1 0 0.5 2-8 Analog Devices B Equations In the following equations: Vgs = intrinsic gate-intrinsic source voltage Vgd = intrinsic gate-intrinsic drain voltage Vds = intrinsic drain-intrinsic source voltage Vt = k·T/q (thermal voltage) k = Boltzmann constant q = electron charge T = analysis temperature (°K) Tnom = nominal temperature (set using .OPTIONS TNOM=) These equations describe an N-channel GaAsFET. Positive current is current flowing into a terminal (for example, positive drain current flows from the drain through the channel to the source). B GaAsFET 2-9 DC Currents Ig = gate current = area·(Igs+Igd) Igs = gate-source leakage current Igd = gate-drain leakage current Vgs/(N·Vt) -1) Igs = IS·(e Vgd/(N·Vt Igd = IS·(e ) -1) Equations for Idrain: LEVEL=1 For: Vds ≥ 0 (normal mode) and: Vgs - VTO < 0 (cutoff region) Idrain = 0 and: Vgs - VTO ≥ 0 (linear & saturation region) Idrain = BETA·(1+LAMBDA·Vds)·(Vgs-VTO)2 ·tanh(ALPHA·Vds) For: Vds < 0 (inverted mode) Switch the source and drain in equations (above). Equations for Idrain: LEVEL=2 For: Vds ≥ 0 (normal mode) and: Vgs - VTO < 0 (cutoff region) Idrain = 0 and: Vgs - VTO ≥ 0 (linear & saturation region) Idrain = BETA·(1+LAMBDA·Vds)·(Vgs-VTO)2 ·Kt/(1+B·(Vgs-VTO)) where Kt (a polynomial approximation of tanh) is: for: 0 < Vds < 3/ALPHA (linear region) Kt = 1 - (1 - Vds·ALPHA/3)3 for: Vds ≥ 3/ALPHA (saturation region) Kt = 1 For: Vds < 0 (inverted mode) Switch the source and drain in equations (above). 2-10 Analog Devices Capacitance1 Cds = drain-source capacitance = area·CDS Equations for Cgs and Cgd: LEVEL=1 Cgs = gate-source capacitance For: Vgs ≤ FC·VBI Cgs = area·CGS·(1-Vgs/VBI) -M For: Vgs > FC·VBI Cgs = area·CGS·(1-FC) -(1+M) ·(1-FC·(1+M)+M·Vgs/VBI) Cgd = gate-drain capacitance For: Vgd ≤ FC·VBI Cgd = area·CGD·(1-Vgd/VBI) -M For: Vgd > FC·VBI Cgd = area·CGD·(1-FC) -(1+M) ·(1-FC·(1+M)+M·Vgd/VBI) Equations for Cgs and Cgd: LEVEL=2 Cgs = gate-source capacitance = area·(CGS·K2·K1/(1-Vn/VBI)1/2 + CGD·K3) Cgd = gate-drain capacitance = area·(CGS·K3·K1/(1-Vn/VBI)1/2 + CGD·K2) where K1 = (1 + (Ve-VTO)/((Ve-VTO)2 +VDELTA 2 ) 1/2 )/2 K2 = (1 + (Vgs-Vgd)/((Vgs-Vgd)2 +(1/ALPHA)2 ) 1/2 )/2 K3 = (1 - (Vgs-Vgd)/((Vgs-Vgd)2+(1/ALPHA)2 ) 1/2 )/2 Ve = (Vgs + Vgd + ((Vgs-Vgd)2 +(1/ALPHA)2 ) 1/2 )/2 If: (Ve + VTO + ((Ve-VTO)2 +VDELTA 2 ) 1/2 )/2 < VMAX Vn = (Ve + VTO + ((Ve-VTO)2 +VDELTA 2 ) 1/2 )/2 else: Vn = VMAX 1. All capacitances are between terminals of the intrinsic GaAsFET (that is, to the inside of the ohmic drain, source, and gate resistances). B B GaAsFET 2-11 Temperature Effects For all levels: VTO(T) = VTO+VTOTC·(T-Tnom) BETA(T) = BETA·1.01 BETATCE·(T-Tnom) IS(T) = IS·e (T/Tnom-1)·EG/(N·Vt) ·(T/Tnom)XTI/N VBI(T) = VBI·T/Tnom - 3·Vt·ln(T/Tnom) - EG(Tnom)·T/Tnom + EG(T) where EG(T) = silicon bandgap energy = 1.16 - .000702·T 2 /(T+1108) CGS(T) = CGS·(1+M·(.0004·(T-Tnom)+(1-VBI(T)/VBI))) CGD(T) = CGD·(1+M·(.0004·(T-Tnom)+(1-VBI(T)/VBI))) Noise Noise is calculated assuming a one hertz bandwidth, using the following spectral power densities (per unit bandwidth): the parasitic resistances, RS, RD, and RG generate thermal noise ... 2 Is = 4·k·T/(RS/area) 2 Id = 4·k·T/(RD/area) 2 Ig = 4·k·T/RG the intrinsic GaAsFET generates shot and flicker noise ... 2 Id = 4·k·T·gm·2/3 + KF·Id AF /FREQUENCY where gm = dIdrain/dVgs (at the DC bias point) 2-12 Analog Devices B References For more information on this GaAsFET model, refer to: [1] W. R. Curtice, “A MESFET model for use in the design of GaAs integrated circuits,” IEEE Transactions on Microwave Theory and Techniques, MTT-28, 448456 (1980). [2] S. E. Sussman-Fort, S. Narasimhan, and K. Mayaram, “A complete GaAs MESFET computer model for SPICE,” IEEE Transactions on Microwave Theory and Techniques, MTT-32, 471-473 (1984). [3] H. Statz, P. Newman, I. W. Smith, R. A. Pucel, and H. A. Haus, “GaAs FET Device and Circuit Simulation in SPICE,” IEEE Transactions on Electron Devices, ED-34, 160-169 (1987). [4] A. J. McCamant, G. D. McCormack, and D. H. Smith, “An Improved GaAs MESFET Model for SPICE,” IEEE Transactions on Microwave Theory and Techniques, June 1990 (est). [5] A. E. Parker and D. J. Skellern “Improved MESFET Characterization for Analog Circuit Design and Analysis,” 1992 IEEE GaAs IC Symposium Technical Digest, pp. 225-228, Miami Beach, October 4-7, 1992. [6] A. E. Parker, “Device Characterization and Circuit Design for High Performance Microwave Applications,” IEE EEDMO’93, London, October 18, 1993. [7] D. H. Smith, “An Improved Model for GaAs MESFETs,” Publication forthcoming. (Copies available from TriQuint Semiconductors Corporation or MicroSim.) C Capacitor 2-13 Capacitor General Form C<name> <(+) node> <(-) node> [model name] <value> + Examples [IC=<initial value>] CLOAD 15 0 20pF C2 1 2 .2E-12 IC=1.5V CFDBCK 3 33 CMOD 10pF Model Form .MODEL <model name> CAP [ model parameters] Table 2-3 Capacitor Model Parameters Model Parameters* Description C Capacitance multiplier VC1 Linear voltage coefficient volt -1 0 VC2 Quadratic voltage coefficient volt -2 0C TC1 Linear temperature coefficient °C -1 0 TC2 Quadratic temperature coefficient °C -2 0 (+) and (-) nodes Units Default 1 Define the polarity when the capacitor has a positive voltage across it. The first node listed (or pin one in Schematics), is defined as positive. The voltage across the component is therefore defined as the first node voltage less the second node voltage. Positive current flows from the (+) node through the capacitor to the (-) node. Current flow from the first node through the component to the second node is considered positive 2-14 Analog Devices [model name] C If [model name]is left out then <value> is the capacitance in farads. If [model name] is specified, then the capacitance is given by the formula <value>·C·(1+VC1·V+VC2·V 2 )·(1+TC1·(T-Tnom)+TC2·(T-Tnom)2 ) where <value> is normally positive (though it can be negative, but not zero). “Tnom” is the nominal temperature (set using TNOM option). <initial value> The initial voltage across the capacitor during the bias point calculation. It can also be specified in a circuit file using a .IC command as follows: .IC V(+node, -node) <initial value> For details on using the .IC command in a circuit file, see page 1-12 of this manual, and refer to your PSpice user’s guide, for more information. Noise The capacitor does not have a noise model. D Diode 2-15 Diode General Form D<name> <(+) node> <(-) node> <model name> [area value] Examples DCLAMP 14 0 DMOD D13 15 17 SWITCH 1.5 Model Form .MODEL < model name> D [ model parameters] Figure 2-2 Diode Model As shown, the diode is modeled as an ohmic resistance (RS/area) in series with an intrinsic diode. The < (+) node> is the anode and <(-) node> is the cathode. Positive current is current flowing from the anode through the diode to the cathode. The [area value] scales IS, ISR, IKF,RS, CJO, and IBV, and defaults to 1. IBV and BV are both specified as positive values.D 2-16 Analog Devices D Model Parameters Table 2-4 Diode Model Parameters Model Parameters* Description Unit Default amp 1E-14 IS Saturation current N Emission coefficient ISR Recombination current parameter NR Emission coefficient for ISR IKF High-injection “knee” current amp infinite BV Reverse breakdown “knee” voltage volt infinite IBV Reverse breakdown “knee” current amp 1E-10 RS Parasitic resistance ohm 0 TT Transit time sec 0 CJO Zero-bias p-n capacitance farad 0 VJ p-n potential volt 1 M p-n grading coefficient 0.5 FC Forward-bias depletion capacitance coefficient 0.5 EG Bandgap voltage (barrier height) XTI IS temperature exponent 1 amp 0 2 eV 1.11 3 TIKF IKF temperature coefficient (linear) °C -1 TRS1 RS temperature coefficient (linear) °C -1 0 TRS2 RS temperature coefficient (quadratic) °C -2 0 KF Flicker noise coefficient 0 AF Flicker noise exponent 1 D 0 Diode 2-17 Equations In the following equations: Vd = voltage across the intrinsic diode only Vt = k·T/q (thermal voltage) k = Boltzmann’s constant q = electron charge T = analysis temperature (°K) Tnom = nominal temperature (set using TNOM option) Other variables are from the model parameter list. DC Current Id = area·(Ifwd - Irev) Ifwd = forward current = Inrm·Kinj + Irec·Kgen Vd/(N·Vt) Inrm = normal current = IS·(e -1) Kinj = high-injection factor For: IKF > 0 1/2 Kinj = (IKF/(IKF+Inrm)) otherwise Kinj = 1 Vd/(NR·Vt) Irec = recombination current = ISR·(e -1) 2 M/2 Kgen = generation factor = ((1-Vd/VJ) +0.005) Irev = reverse current = Irevhigh + Irevlow -(Vd+BV)/(NBV·Vt) Irevhigh = IBV·e -(Vd+BV)/(NBVL·Vt) Irevlow = IBVL·e Capacitance Cd = Ct + area·Cj Ct = transit time capacitance = TT·Gd where Gd = DC conductance Cj = junction capacitance For: Vd ≤ FC·VJ -M Cj = CJO·(1-Vd/VJ) For: Vd > FC·VJ -(1+M) Cj = CJO·(1-FC) ·(1-FC·(1+M)+M·Vd/VJ) 2-18 Analog Devices E/G Voltage-Controlled Voltage Source and Voltage-Controlled Current Source Note The Voltage-Controlled Voltage Source (E) and the VoltageControlled Current Source (G) devices have the same syntax. For a Voltage-Controlled Current Source just substitute a “G” for the “E”. The “G” device generates a current, whereas, the “E” device generates a voltage. General Form E<name> <(+) node> <(-) node> <(+) controlling node> <(-) controlling node> <gain> E<name> <(+) node> <(-) node> POLY(<value>) + < <(+) controlling node> <(-) controlling node> >* + < <polynomial coefficient value> >* E<name> <(+) <node> <(-) node> VALUE = { <expression> } E<name> <(+) <node> <(-) node> TABLE { <expression> } = + < <input value>,<output value> >* E<name> <(+) node> <(-) node> LAPLACE { <expression> } = + { <transform> } E<name> <(+) node> <(-) node> FREQ { <expression> } = [KEYWORD] + < <frequency value>,<magnitude value>,<phase value> >* + [DELAY = <delay value>] Examples EBUFF 1 2 10 11 1.0 EAMP 13 0 POLY(1) 26 0 0 500 ENONLIN 100 101 POLY(2) 3 0 4 0 0.0 13.6 0.2 0.005 The first form and the first two examples apply to the linear case. The second form and the last example are for the nonlinear case. E/G Voltage-Controlled Voltage Source and Voltage-Controlled Current Source POLY(<value>) 2-19 Specifies the number of dimensions of the polynomial. The number of pairs of controlling nodes must be equal to the number of dimensions. (+) and (-) nodes Output nodes. Positive current flows from the (+) node through the source to the (-) node. The <(+) controlling node> and <(-) controlling node> are in pairs and define a set of controlling voltages. A particular node can appear more than once, and the output and controlling nodes need not be different. The TABLE form has a maximum size of 2048 input/output value pairs. For the linear case, there are two controlling nodes and these are followed by the gain. For all cases, including the nonlinear case (POLY), refer to your PSpice user’s guide. Expressions cannot be used for linear and polynomial coefficient values in a voltage-controlled voltage source device statement. 2-20 Analog Devices F/H Current-Controlled Current Source and Current-Controlled Voltage Source Note The Current-Controlled Current Source (F) and the CurrentControlled Voltage Source (H) devices have the same syntax. For a Current-Controlled Voltage Source just substitute a “H” for the “F”. The “H” device generates a voltage, whereas, the “F” device generates a current. General Form F<name> <(+) node> <(-) node> + <controlling V device name> <gain> F<name> <(+) node> <(-) node> POLY(<value>) + <controlling V device name>* + < <polynomial coefficient value> >* (+) and (-) These nodes are the output nodes. A positive current flows from the (+) node through the source to the (-) node. The current through the controlling voltage source determines the output current. The controlling source must be an independent voltage source (V device), although it need not have a zero DC value. For the linear case, there must be one controlling voltage source and its name is followed by the gain. For all cases, including the nonlinear case (POLY), refer to your PSpice user’s guide. Note Examples Expressions cannot be used for linear and polynomial coefficient values in a current-controlled current source device statement. FSENSE 1 2 VSENSE 10.0 FAMP 13 0 POLY(1) VIN 0 500 FNONLIN 100 101 POLY(2) VCNTRL1 VCINTRL2 0.0 13.6 0.2 0.005 The first form and the first two Examples apply to the linear case. The second form and the last example are for the nonlinear case. POLY(<value>) specifies the number of dimensions of the polynomial. The number of controlling voltage sources must be equal to the number of dimensions.F/H I/V Independent Current Source & Stimulus and Independent Voltage Source & Stimulus 2-21 Independent Current Source & Stimulus and Independent Voltage Source & Stimulus Note The Independent Current Source & Stimulus (I) and the Independent Voltage Source & Stimulus (V) devices have the same syntax. For an Independent Voltage Source & Stimulus just substitute a “V” for the “I”. The “V” device functions identically and has the same syntax as the “I” device, except that it generates voltage instead of current. General Form Examples I<name> <(+) node> <(-) node> + [ [DC] <value> ] + [ AC <magnitude value> [phase value] ] + [transient specification] IBIAS 13 IAC 2 IACPHS 2 IPULSE 1 I3 26 0 3 3 0 77 2.3mA AC .001 AC .001 90 PULSE(-1mA 1mA 2ns 2ns 2ns 50ns 100ns) DC .002 AC 1 SIN( .002 .002 1.5MEG) This element is a current source. Positive current flows from the (+) node through the source to the (-) node: in the first example, IBIAS drives node 13 to have a negative voltage. The default value is zero for the DC, AC, and transient values. None, any, or all of the DC, AC, and transient values can be specified. The AC phase value is in degrees. The pulse and exponential examples are explained later in this section. [transient specification] If present, they must be one of: EXP (<parameters>) for an exponential waveform PULSE (<parameters>) for a pulse waveform PWL (<parameters>) for a piecewise linear waveform SFFM (<parameters>) for a frequency-modulated waveform SIN (<parameters>) for a sinusoidal waveform I/V 2-22 Analog Devices I/V The variables TSTEP and TSTOP, which are used in defaulting some waveform parameters, are set by the .TRAN command. TSTEP is <print step value> and TSTOP is <final time value>. The .TRAN command can be anywhere in the circuit file; it need not come after the voltage source. Independent Current Source & Stimulus (EXP) General Form EXP (<i1> <i2> <td1> <tc1> <td2> <tc2>) Example IRAMP 10 5 EXP(1 5 1 .2 2 .5) Table 2-5 Independent Current Source and Stimulus Exponential Waveform Parameters Parameters Description Units Default <i1> Initial current amp none <i2> Peak current amp none <td1> Rise (fall) delay sec 0 <tc1> Rise (fall) time constant sec TSTEP <td2> Fall (rise) delay sec <td1>+TSTEP <tc2> Fall (rise) time constant sec TSTEP The EXP form causes the current to be <i1> for the first <td1> seconds. Then, the current decays exponentially from <i1> to <i2> using a time constant of <tc1>. The decay lasts td2-td1 seconds. Then, the current decays from <i2> back to <i1> using a time constant of <tc2>. Independent Current Source & Stimulus (PULSE) General Form PULSE (<i1> <i2> <td> <tr> <tf> <pw> <per>) Examples ISW 10 5 PULSE(1A 5A 1sec .1sec .4sec .5sec 2sec) I/V Independent Current Source & Stimulus and Independent Voltage Source & Stimulus 2-23 Table 2-6 Independent Current Source and Stimulus Pulse Waveform Parameters Parameters Description Units Default <i1> Initial current amp none <i2> Pulsed current amp none <per> Period sec TSTOP <pw> Pulse width sec TSTOP <td> Delay sec 0 <tf> Fall time sec TSTEP <tr> Rise time sec TSTEP The PULSE form causes the current to start at <i1>, and stay there for <td> seconds. Then, the current goes linearly from <i1> to <i2> during the next <tr> seconds, and then the current stays at <i2> for <pw> seconds. Then, it goes linearly from <i2> back to <i1> during the next <tf> seconds. It stays at <i1> for per-(tr+pw+tf) seconds, and then the cycle is repeated except for the initial delay of <td> seconds. Independent Current Source & Stimulus (PWL) General Form PWL (corner_points) where corner_points are: (<tn>, <in>) Examples I1 1 2 PWL (0 1 1.2 5 1.4 2 2 4 3 1) Table 2-7 Independent Voltage Source and Stimulus PWL Waveform Parameters Parameters* Description Units Default <tn> Time at corner seconds None <vn> Voltage at corner volts None 2-24 Analog Devices I/V The PWL form describes a piecewise linear waveform. Each pair of time-current values specifies a corner of the waveform. The current at times between corners is the linear interpolation of the currents at the corners. Independent Current Source & Stimulus (SFFM) General Form SFFM (<ioff> <iampl> <fc> <mod> <fm>) Examples IMOD 10 5 SFFM(2 1 8Hz 4 1Hz) Table 2-8 Independent Current Source and Stimulus Frequency- Modulated Waveform Parameters Parameter Description Units Default <ioff> Offset current amp none <iampl> Peak amplitude of current amp none <fc> Carrier frequency hertz 1/TSTOP <mod> Modulation index <fm> Modulation frequency 0 hertz 1/TSTOP The SFFM (Single-Frequency FM) form causes the current, to follow this formula ioff + iampl·sin(2π·fc·TIME + mod·sin(2π·fm·TIME)) Independent Current Source & Stimulus (SIN) General Form SIN (<ioff> <iampl> <freq> <td> <df> <phase>) Examples ISIG 10 5 SIN(2 2 5Hz 1sec 1 30) I/V Independent Current Source & Stimulus and Independent Voltage Source & Stimulus 2-25 Table 2-9 Independent Current Source and Stimulus Sinusoidal Waveform Parameters Parameters Description Units Default <ioff> Offset current amp none <iampl> Peak amplitude of current amp none <freq> Frequency hertz 1/TSTOP <td> Delay sec 0 <df> Damping factor sec <phase> Phase degree -1 0 0 The sinusoidal (SIN) waveform causes the current to start at <ioff> and stay there for <td> seconds. Then, the current becomes an exponentially damped sine wave. The waveform could be described by the following formulas. -(TIME-td)·df ioff+iampl·sin(2π·(freq·(TIME-td)+phase/360°))·e Note The SIN waveform is for transient analysis only. It does not have any effect during AC analysis. To give a value to a current during AC analysis, use an AC specification, such as IAC 3 0 AC 1mA where IAC has an amplitude of one milliampere during AC analysis, and can be zero during transient analysis. For transient analysis use (for example) ITRAN 3 0 SIN(0 1mA 1kHz) where ITRAN has an amplitude of one milliampere during transient analysis and is zero during AC analysis. Refer to your PSpice user’s guide. 2-26 Analog Devices J Junction FET General Form J<name> <drain node> <gate node> <source node> + <model name> [area value] Examples JIN 100 1 0 JFAST J13 22 14 23 JNOM 2.0 Model Form .MODEL <model name> NJF [ model parameters] .MODEL <model name> PJF [ model parameters] Figure 2-3 JFET Model As shown in Figure 2-3, the JFET is modeled as an intrinsic FET using an ohmic resistance (RD/area) in series with the drain, and using another ohmic resistance (RS/area) in series with the source. Positive current is current flowing into a terminal. The [area value] is the relative device area and defaults to 1.J J Junction FET 2-27 Table 2-10 Junction FET Model Parameters Model Parameters Description AF Flicker noise exponent ALPHA Ionization coefficient volt BETA Transconductance coefficient amp/volt BETATCE BETA exponential temperature coefficient %/°C 0 CGD Zero-bias gate-drain p-n capacitance farad 0 CGS Zero-bias gate-source p-n capacitance farad 0 FC Forward-bias depletion capacitance coefficient IS Gate p-n saturation current amp 1E-14 ISR Gate p-n recombination current parameter amp 0 KF Flicker noise coefficient LAMBDA Channel-length modulation M Gate p-n grading coefficient N Gate p-n emission coefficient 1 NR Emission coefficient for ISR 2 PB Gate p-n potential volt RD Drain ohmic resistance ohm 0 RS Source ohmic resistance ohm 0 VK Ionization “knee” voltage volt 0 VTO Threshold voltage volt -2.0 VTOTC VTO temperature coefficient volt/°C XTI IS temperature coefficient Note Units Default 1 -1 0 2 1E-4 0.5 0 volt -1 0 0.5 VTO < 0 means the device is a depletion-mode JFET (for both Nchannel and P-channel) and VTO > 0 means the device is an enhancement-mode JFET. This conforms to U.C. Berkeley SPICE. 1.0 0 3 2-28 Analog Devices J Equations In the following equations: Vgs = intrinsic gate-intrinsic source voltage Vgd = intrinsic gate-intrinsic drain voltage Vds = intrinsic drain-intrinsic source voltage Vt = k·T/q (thermal voltage) k = Boltzmann’s constant q = electron charge T = analysis temperature (°K) Tnom = nominal temperature (set using TNOM option) Other variables are from the model parameter list. These equations describe an Nchannel JFET. For P-channel devices, reverse the sign of all voltages and currents. DC Currents Note Positive current is current flowing into a terminal. Ig = gate current = area·(Igs + Igd) Igd = gate-drain leakage current = In + Ir·Kg + Ii In = normal current = IS·(e Vgd/(N·Vt) Ir = recombination current = ISR·(e -1) Vgd/(NR·Vt) 2 -1) Kg = generation factor = ((1-Vgd/PB) +0.005) M/2 Ii = impact ionization current For: 0 < Vgs-VTO < Vds (forward saturation region) Ii = Idrain·ALPHA·vdif·e -VK/vdif where vdif = Vds - (Vgs-VTO) otherwise Ii = 0 Id = drain current = area·(-Idrain-Igd) Is = source current = area·(Idrain-Igs) J Junction FET 2-29 Equation for Idrain For: Vds ≥ 0 (normal mode) and: Vgs-VTO ≤ 0 (cutoff region) Idrain = 0 and: Vds ≤ Vgs-VTO (linear region) Idrain = BETA·(1+LAMBDA·Vds)·Vds·(2·(Vgs-VTO)-Vds) and: 0 < Vgs-VTO < Vds (saturation region) Idrain = BETA·(1+LAMBDA·Vds)·(Vgs-VTO) For: Vds < 0 2 (inverted mode) Switch the source and drain in equations (above). Capacitance Note All capacitances are between terminals of the intrinsic JFET (that is, to the inside of the ohmic drain and source resistances). Cgs = gate-source depletion capacitance For: Vgs ≤ FC·PB Cgs = area·CGS·(1-Vgs/PB) -M For: Vgs > FC·PB Cgs = area·CGS·(1-FC) -(1+M) ·(1-FC·(1+M)+M·Vgs/PB) Cgd = gate-drain depletion capacitance For: Vgd ≤ FC·PB Cgd = area·CGD·(1-Vgd/PB) -M For: Vgd > FC·PB Cgd = area·CGD·(1-FC) -(1+M) ·(1-FC·(1+M)+M·Vgd/PB) 2-30 Analog Devices J Temperature Effects VTO(T) = VTO+VTOTC·(T-Tnom) BETA(T) = BETA·1.01 IS(T) = IS·e BETATCE·(T-Tnom) (T/Tnom-1)·EG/(N·Vt) ·(T/Tnom) XTI/N where EG = 1.11 ISR(T) = ISR·e (T/Tnom-1)·EG/(NR·Vt) ·(T/Tnom) XTI/NR where EG = 1.11 PB(T) = PB·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) where Eg(T) = silicon bandgap energy = 1.16 - .000702·T 2 /(T+1108) CGS(T) = CGS·(1+M·(.0004·(T-Tnom)+(1-PB(T)/PB))) CGD(T) = CGD·(1+M·(.0004·(T-Tnom)+(1-PB(T)/PB))) The drain and source ohmic (parasitic) resistances have no temperature dependence. Noise Noise is calculated assuming a one hertz bandwidth, using the following spectral power densities (per unit bandwidth): the parasitic resistances, Rs and Rd, generate thermal noise ... Is Id 2 2 = 4·k·T/(RS/area) = 4·k·T/(RD/area) the intrinsic JFET generates shot and flicker noise ... Idrain 2 = 4·k·T·gm·2/3 + KF·Idrain AF /FREQUENCY where gm = dIdrain/dVgs (at the DC bias point) K Inductor Coupling (transformer core) 2-31 Inductor Coupling (transformer core) General Form K<name> L<inductor name> < L<inductor name> >* + <coupling value> K<name> < L<inductor name> >* <coupling value> + <model name> [size value] Examples KTUNED L3OUT L4IN .8 KTRNSFRM LPRIMARY LSECNDRY .99 KXFRM L1 L2 L3 L4 Model Form .98 KPOT_3C8 .MODEL < model name> CORE [ model parameters] This device can be used to define coupling between inductors (transformers). This device also refers to a nonlinear magnetic core (CORE) model to include magnetic hysteresis effects in the behavior of a single inductor (winding), or in multiple coupled windings. Table 2-11 Inductor Coupling Model Parameters Model Description Parameters* A Thermal energy parameter AREA Mean magnetic cross-section Units Default amp/meter 1E+3 cm 2 0.1 C Domain flexing parameter GAP Effective air-gap length K Domain anisotropy parameter amp/meter 500 MS Magnetization saturation 1E+6 PACK Pack (stacking) factor 1.0 PATH Mean magnetic path length K cm 1.0 *See .MODEL statement. 0.2 cm amp/meter 0 2-32 Analog Devices K Inductor Coupling K<name> couples two, or more, inductors. Using the “dot” convention, place a “dot” on the first node of each inductor. In other words, given: I1 L1 L2 R2 K12 1 1 2 2 L1 0 0 0 0 L2 AC 1mA 10uH 10uH .1 .9999 the current through L2 is in the opposite direction as the current through L1. The polarity is determined by the order of the nodes in the L device(s) and not by the order of inductors in the K statement. <coupling value> This is the “coefficient of mutual coupling” which must be between 0 and 1. Note that iron-core transformers have a very high coefficient of coupling, greater than .999 in many cases. For U.C. Berkeley SPICE2: if there are several coils on a transformer, then there must be K statements coupling all combinations of inductor pairs. For instance, a transformer using a center-tapped primary and two secondaries would be written: * PRIMARY L1 1 2 10uH L2 2 3 10uH * SECONDARY L3 11 12 10uH L4 13 14 10uH * MAGNETIC COUPLING K12 L1 L2 1 K13 L1 L3 1 K14 L1 L4 1 K23 L2 L3 1 K24 L2 L4 1 K34 L3 L4 1 This “older” technique is still supported, but not required, for simulation. The same transformer can now be written: K Inductor Coupling (transformer core) 2-33 * PRIMARY L1 1 2 10uH L2 2 3 10uH * SECONDARY L3 11 12 10uH L4 13 14 10uH * MAGNETIC COUPLING KALL L1 L2 L3 L4 1 Note Do not mix the two techniques. <model name> If < model name> is present, four things change: 1 The mutual coupling inductor becomes a nonlinear, magnetic core device. The magnetic core’s B-H characteristics are analyzed using the Jiles-Atherton model (see Reference [1] below). 2 The inductors become “windings,” so the number specifying inductance now specifies the “number of turns.” 3 The list of coupled inductors could be just one inductor. 4 A model statement is required to specify the model parameters. [size value] Defaults to one and scales the magnetic cross-section. It is intended to represent the number of lamination layers, so only one model statement is needed for each lamination type. For example L1 5 9 20 ; inductor having 20 turns K1 L1 .9999 K528T500_3C8 ; Ferroxcube toroid core L2 3 8 15 ; primary winding having 15 turns L3 4 6 45 ; secondary winding having 45 turns K2 L2 L3 .9999 K528T500_3C8 ; another core (not the same as K1) The Jiles-Atherton model is based on existing ideas of domain wall motion, including flexing and translation. The model derives an anhysteric magnetization curve using a mean field technique in which any domain is coupled to the magnetic field (H) and the bulk magnetization (M). This anhysteric value is the magnetization which would be reached in the absence of domain wall pinning. Hysteresis is modeled by the effects of pinning of domain walls on material defect sites. This 2-34 Analog Devices K impedance to motion and flexing due to the differential field exhibits all of the main features of real, nonlinear magnetic devices, such as: the initial magnetization curve (initial permeability), saturation of magnetization, coercivity, remanence, and hysteresis loss. These features are shown in Figure 2-4. Figure 2-4 Probe B-H display of 3C8 ferrite (Ferroxcube) The simulator uses the Jiles-Atherton model to analyze the B-H curve of the magnetic core, and calculate values for inductance and flux for each of the “windings.” The state of the nonlinear core can be viewed in Probe by specifying B(Kxxx), for the magnetization, or H(Kxxx), for the magnetizing influence. These values are not available for .PRINT or .PLOT output. Reference For a description of the Jiles-Atherton model, refer to: [1] D.C. Jiles, and D.L. Atherton, “Theory of ferromagnetic hysteresis,” Journal of Magnetism and Magnetic Materials, 61, 48 (1986). L Inductor 2-35 Inductor General Form L<name> <(+) node> <(-) node> [model name] <value> + [IC=<initial value>] Examples LLOAD 15 0 20mH L2 1 2 .2E-6 LCHOKE 3 42 LMOD .03 LSENSE 5 12 2UH IC=2mA Model Form .MODEL < model name> IND [ model parameters] Table 2-12 Model Parameters* L IL1 IL2 TC1 TC2 Inductor Model Parameters Description Units Inductance multiplier Linear current coefficient Quadratic current coefficient Linear temperature coefficient Quadratic temperature coefficient amp -2 amp -1 °C -2 °C -1 Default 1 0 0 0 0 * see the .MODEL statement (+) and (-) The (+) and (-) nodes define the polarity when the inductor has a positive voltage across it. Positive current flows from the (+) node through the inductor to the (-) node. [model name] If [model name] is left out, then the effective value is <value>. If [model name] is specified, then the effective value is given by the formula 2 2 <value>·L·(1+IL1·I+IL2·I )·(1+TC1·(T-Tnom)+TC2·(T-Tnom) ) where <value> is normally positive (though it can be negative, but not zero). “Tnom” is the nominal temperature (set using TNOM option). <initial value> The initial current through the inductor during the bias point calculation. L Noise The inductor does not have a noise model. 2-36 Analog Devices M MOSFET General Form M<name> <drain node> <gate node> <source node> + <bulk/substrate node> <model name> + [L=<value>] [W=<value>] + [AD=<value>] [AS=<value>] + [PD=<value>] [PS=<value>] + [NRD=<value>] [NRS=<value>] + [NRG=<value>] [NRB=<value>] + [M=<value>] Examples M1 14 2 13 0 PNOM L=25u W=12u M13 15 3 0 0 PSTRONG M16 17 3 0 0 PSTRONG M=2 M28 0 2 100 100 NWEAK L=33u W=12u + AD=288p AS=288p PD=60u PS=60u NRD=14 NRS=24 NRG=10 Model Form .MODEL < model name> .MODEL < model name> Figure 2-5 M NMOS [ model parameters] PMOS [ model parameters] MOSFET Model M Mosfet 2-37 As shown in Figure Model Form, the MOSFET is modeled as an intrinsic MOSFET using ohmic resistances in series with the drain, source, gate, and bulk (substrate). There is also a shunt resistance (RDS) in parallel with the drain-source channel. The simulator provides four MOSFET device models, which differ in the formulation of the I-V characteristic. The LEVEL parameter selects between different models: Table 2-13 MOSFET Levels MOSFET LEVELS LEVEL=1 LEVEL=2 LEVEL=3 LEVEL=4 L and W Model Definition Shichman-Hodges model (see reference [1]) geometry-based, analytic model (see reference [2]) semi-empirical, short-channel model (see reference [2]) BSIM model (see reference [3]) These are the channel length and width, and are decreased to get the effective channel length and width. L and W can be specified in the device, model, or .OPTIONS statements. The value in the device statement supersedes the value in the model statement, which supersedes the value in the .OPTIONS statement. AD and AS These are the drain and source diffusion areas. PD and PS These are the drain and source diffusion perimeters. The drain-bulk and source-bulk saturation currents can be specified either by JS, which is multiplied by AD and AS, or by IS, which is an absolute value. The zero-bias depletion capacitances can be specified by CJ, which is multiplied by AD and AS, and by CJSW, which is multiplied by PD and PS. Or they can be set by CBD and CBS, which are absolute values. 2-38 Analog Devices M NRD, NRS, NRG, and NRB These are the relative resistivities of the drain, source, gate, and substrate in squares. These parasitic (ohmic) resistances can be specified either by RSH, which is multiplied by NRD, NRS, NRG, and NRB respectively or by RD, RS, RG, and RB, which are absolute values. PD and PS default to 0, NRD and NRS default to 1, and NRG and NRB default to 0. Defaults for L, W, AD, and AS can be set in the .OPTIONS statement. If AD or AS defaults are not set, they also default to 0. If L or W defaults are not set, they default to 100u. M Device “multiplier” (default = 1), which simulates the effect of multiple devices in parallel. The effective width, overlap and junction capacitances, and junction currents of the MOSFET are multiplied by M. The parasitic resistance values (e.g., RD and RS) are divided by M. Note the third example showing a device twice the size of the second example. Model Levels 1, 2, and 3 The DC characteristics of the first three model levels are defined by the parameters VTO, KP, LAMBDA, PHI, and GAMMA. These are computed by the simulator if process parameters (e.g., TOX, and NSUB) are given, but the user-specified values always override (Note: The default value for TOX is 0.1 µ for model levels two and three, but is unspecified for level one which “turns off” the use of process parameters). VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode of N-channel (P-channel) devices. M Mosfet 2-39 Table 2-14 MOSFET Level 1, 2, and 3 Model Parameters Model Parameters* DELTA Description ETA Static feedback (LEVEL=3) Units Default Width effect on threshold 0 0 1/2 GAMMA Bulk threshold parameter volt KP Transconductance coefficient amp/volt KAPPA Saturation field factor (LEVEL=3) LAMBDA LD Channel-length modulation (LEVEL=1 or 2) Lateral diffusion (length) 2 0.2 0 meter 0 volt NFS 1/cm NSS Surface state density 1/cm NSUB Substrate doping density 1/cm PHI Surface potential volt 1.0 2 0 2 none 3 none 0.6 -1 THETA Mobility modulation (LEVEL=3) volt TOX Oxide thickness meter TPG Gate material type: +1 = opposite of substrate -1 = same as substrate 0 = aluminum +1 UCRIT Mobility degradation critical field (LEVEL=2) Mobility degradation exponent (LEVEL=2) (not used) Mobility degradation transverse field coefficient Surface mobility. (The second character is the letter O, not the numeral zero.) UEXP UTRA UO 2E-5 -1 Channel charge coefficient (LEVEL=2) Fast surface state density NEFF calculated 0 see above +1 volt/cm 1E4 0 0 2 cm /volt· 600 sec VMAX Maximum drift velocity meter/sec 0 VTO Zero-bias threshold voltage volt 0 WD Lateral diffusion (width) meter 0 meter 0 Metallurgical junction depth (LEVEL=2 or 3) Fraction of channel charge XQC attributed to drain * See .MODEL statement. XJ 1.0 2-40 Analog Devices M Model Level 4 The LEVEL=4 (BSIM1) model parameters are all values obtained from process characterization, and can be generated automatically. Reference [4] describes a means of generating a “process” file, which mut then be converted into .MODEL statements for inclusion in the Model Library or circuit file. (The simulator does not read process files.) In the following list, parameters marked using a “ζ” in the L&W column also have corresponding parameters with a length and width dependency. For example, VFB is a basic parameter using units of volts, and LVFB and WVFB also exist and have units of volt·µ. The formula Pi = P0 + PL/Le + PW /W e is used to evaluate the parameter for the actual device, where Le = effective length = L - DL W e = effective width = W - DW Note Unlike the other models in PSpice, the BSIM model is designed for use with a process characterization system that provides all parameters: there are no defaults specified for the parameters, and leaving one out can cause problems. Table 2-15 MOSFET Level 4 Model Parameters Model Parameters* DELL Description Units Drain, source junction length reduction meter DL Channel shortening µ DW Channel narrowing µ ETA Zero-bias drain-induced barrier lowering coefficient K1 Body effect coefficient K2 Drain/source depletion charge sharing coefficient MUS Mobility at zero substrate bias and Vds=Vdd L&W ζ volt ½ ζ ζ 2 2 cm /v ·sec ζ M Mosfet 2-41 MUZ Zero-bias mobility N0 Zero-bias subthreshold slope coefficient Sens. of subthreshold slope to substrate bias Sens. of subthreshold slope to drain bias Surface inversion potential NB ND PHI TEMP TOX Temperature at which parameters were measured Gate-oxide thickness 2 cm /v·sec ζ ζ ζ ζ volt °C µ -1 ζ µ/volt ζ volt U1 Zero-bias transverse-field mobility degradation Zero-bias velocity saturation VDD Measurement bias range volts VFB Flat-band voltage volt WDF Drain, source junction default width meter U0 Sens. of drain-induced barrier lowering effect to substrate bias Sens. of mobility to substrate bias @ X2MS Vds=0 Sens. of mobility to substrate bias @ X2MZ Vds=0 Sens. of transverse-field mobility X2U0 degradation effect to substrate bias Sens. of velocity saturation effect to X2U1 substrate bias Sens. of drain-induced barrier X3E lowering effect to drain bias @ Vds = Vdd Sens. of mobility to drain bias @ X3MS Vds=Vdd Sens. of velocity saturation effect on X3U1 drain Gate-oxide capacitance charge XPART model flag. XPART=0 selects a 40/60 drain/source charge partition in saturation, while XPART=1 selects a 0/100 drain/source charge partition. *See .MODEL statement X2E volt ζ ζ -1 2 2 cm /v ·sec ζ 2 2 cm /v ·sec ζ volt µ/volt volt ζ -2 2 ζ ζ -1 2 2 cm /v ·sec ζ µ/volt 2 ζ ζ in L&W column indicates that parameter may have corresponding parameters exhibiting length and width dependence. See discussion under Model Level 4 on page 2-40. 2-42 Analog Devices M For All Model Levels The following list describes the parameters common to all model levels, which are primarily parasitic element values such as series resistance, overlap and junction capacitance, and so on. Table 2-16 MOSFET Model Parameters for All Levels Model Parameters* AF CBD CBS CGBO CGDO CGSO CJ CJSW FC IS JS JSSW KF L LEVEL MJ MJSW N PB PBSW RB RD RDS RG RS RSH TT W Description Flicker noise exponent Zero-bias bulk-drain p-n capacitance Zero-bias bulk-source p-n capacitance Gate-bulk overlap capacitance/channel length Gate-drain overlap capacitance/channel width Gate-source overlap capacitance/channel width Bulk p-n zero-bias bottom capacitance/area Bulk p-n zero-bias sidewall capacitance/length Bulk p-n forward-bias capacitance coefficient Bulk p-n saturation current Bulk p-n saturation current/area Bulk p-n saturation sidewall current/length Flicker noise coefficient Channel length Model index Bulk p-n bottom grading coefficient Bulk p-n sidewall grading coefficient Bulk p-n emission coefficient Bulk p-n bottom potential Bulk p-n sidewall potential Bulk ohmic resistance Drain ohmic resistance Drain-source shunt resistance Gate ohmic resistance Source ohmic resistance Drain, source diffusion sheet resistance Bulk p-n transit time Channel width Units Default farad 1 0 farad 0 farad/meter 0 farad/meter 0 farad/meter 0 farad/meter 2 farad/meter 0 0 0.5 amp 2 amp/meter amp/meter meter 1E-14 0 0 0 DEFL 1 0.5 0.33 volt volt ohm ohm ohm ohm ohm ohm/square 1 0.8 PB 0 0 infinite 0 0 0 sec meter 0 DEFW M Mosfet 2-43 Equations In the following equations: Vgs = intrinsic gate-intrinsic source voltage Vgd = intrinsic gate-intrinsic drain voltage Vds = intrinsic drain-intrinsic source voltage Vbs = intrinsic substrate-intrinsic source voltage Vbd = intrinsic substrate-intrinsic drain voltage Vt = k·T/q (thermal voltage) k = Boltzmann’s constant q = electron charge T = analysis temperature (°K) Tnom = nominal temperature (set using TNOM option) Other variables are from the model parameter list. These equations describe an N-channel MOSFET. For P-channel devices, reverse the signs of all voltages and currents. Positive current is current flowing into a terminal (for example, positive drain current flows from the drain through the channel to the source). DC Currents 1 Ig = gate current = 0 Ib = bulk current = Ibs+Ibd Ibs = bulk-source leakage current = Iss·(e Ibd = bulk-drain leakage current = Ids·(e Vbs/(N·Vt) Vbd/(N·Vt) where if: JS = 0, or AS = 0, or AD = 0 Iss = IS Ids = IS otherwise: Iss = AS·JS + PS·JSSW Ids = AD·JS + PD·JSSW Id = drain current = -Idrain+Ibd Is = source current = Idrain+Ids -1) -1) 2-44 Analog Devices M Equations for Idrain: LEVEL=1 For: Vds ≥ 0 (normal mode) and: Vgs-Vto < 0 (cutoff region) Idrain = 0 and: Vds < Vgs-Vto (linear region) Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·Vds·(2·(Vgs-Vto)-Vds) and: 0 ≤ Vgs-Vto ≤ Vds (saturation region) Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·(Vgs-Vto) where Vto = VTO + GAMMA·((PHI-Vbs) For: Vds < 0 1/2 2 -PHI 1/2 ) (inverted mode) Switch the source and drain in equations (above). For LEVEL=2, or LEVEL=3 MOSFET models, see reference [2] on 2-30 for detailed information. 1. Positive current is current flowing into a terminal. Capacitance1 Cbs = bulk-source capacitance = area cap. + sidewall cap. + transit time cap. Cbd = bulk-drain capacitance = area cap. + sidewall cap. + transit time cap. For: CBS = 0 and CBD = 0 Cbs = AS·CJ·Cbsj + PS·CJSW·Cbss + TT·Gbs Cbd = AD·CJ·Cbdj + PD·CJSW·Cbds + TT·Gds otherwise Cbs = CBS·Cbsj + PS·CJSW·Cbss + TT·Gbs Cbd = CBD·Cbdj + PD·CJSW·Cbds + TT·Gds where Gbs = DC bulk-source conductance = dIbs/dVbs Gbd = DC bulk-drain conductance = dIbd/dVbd or: Vbs ≤ FC·PB Cbsj = (1-Vbs/PB) -MJ Cbss = (1-Vbs/PBSW) -MJSW M Mosfet 2-45 For: Vbs > FC·PB Cbsj = (1-FC) -(1+MJ) Cbss = (1-FC) ·(1-FC·(1+MJ)+MJ·Vbs/PB) -(1+MJSW) ·(1-FC·(1+MJSW)+MJSW·Vbs/PBSW) For: Vbd ≤ FC·PB Cbdj = (1-Vbd/PB) -MJ Cbds = (1-Vbd/PBSW) -MJSW For: Vbd > FC·PB Cbdj = (1-FC) Cbds = (1-FC) -(1+MJ) ·(1-FC·(1+MJ)+MJ·Vbd/PB) -(1+MJSW) ·(1-FC·(1+MJSW)+MJSW·Vbd/PBSW) Cgs = gate-source overlap capacitance = CGSO·W Cgd = gate-drain overlap capacitance = CGDO·W Cgb = gate-bulk overlap capacitance = CGBO·L See reference [2] for the equations describing the capacitances due to the channel charge. 1. All capacitances are between terminals of the intrinsic MOSFET. That is, to the inside of the ohmic drain and source resistances. Temperature Effects (Eg(Tnom)·T/Tnom - Eg(T))/V t IS(T) = IS·e JS(T) = JS·e (Eg(Tnom)·T/Tnom - Eg(T))/V t JSSW(T) = JSSW·e (Eg(Tnom)·T/Tnom - Eg(T))/V t = PB·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) PB(T) PBSW(T) PHI(T) = PBSW·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) = PHI·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) 2 where Eg(T) = silicon bandgap energy = 1.16 - .000702·T /(T+1108) CBD(T) = CBD·(1+MJ·(.0004·(T-Tnom)+(1-PB(T)/PB))) CBS(T) = CBS·(1+MJ·(.0004·(T-Tnom)+(1-PB(T)/PB))) CJ(T) = CJ·(1+MJ·(.0004·(T-Tnom)+(1-PB(T)/PB))) CJSW(T) = CJSW·(1+MJSW·(.0004·(T-Tnom)+(1-PB(T)/PB))) -3/2 KP(T) = KP·(T/Tnom) UO(T) = UO·(T/Tnom) MUS(T) -3/2 = MUS·(T/Tnom) -3/2 2-46 Analog Devices MUZ() M = MUZ·(T/Tnom) X3MS(T) -3/2 = X3MS·(T/Tnom) -3/2 The ohmic (parasitic) resistances have no temperature dependence. Noise Noise is calculated assuming a one hertz bandwidth, using the following spectral power densities (per unit bandwidth): the parasitic resistances (Rd, Rg, Rs, and Rb) generate thermal noise ... 2 Id = 4·k·T/Rd 2 Ig = 4·k·T/Rg 2 Is = 4·k·T/Rs 2 Ib = 4·k·T/Rb the intrinsic MOSFET generates shot and flicker noise ... 2 AF Idrain = 4·k·T·gm·2/3 + KF·Idrain /(FREQUENCY·Kchan) where gm = dIdrain/dVgs (at the DC bias point) 2 Kchan = (effective length) ·(permittivity of SiO2)/TOX References For a more complete description of the MOSFET models, refer to: [1] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits,” IEEE Journal of Solid-State Circuits, SC-3, 285, September 1968. [2] A. Vladimirescu, and S. Lui, “The Simulation of MOS Integrated Circuits Using SPICE2,” Memorandum No. M80/7, February 1980. [3] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors,” IEEE Journal of Solid-State Circuits, SC-22, 558-566, August 1987. [4] J. R. Pierret, “A MOS Parameter Extraction Program for the BSIM Model,” Memorandum No. M84/99 and M84/100, November 1984. N Digital input 2-47 Digital Input General Form Example N<name> <interface node> <low level node> <high level node> + <model name> + DGTLNET = <digital net name> + <digital I/O model name> + SIGNAME=<digital signal name> + [IS = initial state] NRESET 7 15 16 FROM_TTL N12 Model Form 18 0 100 FROM_CMOS SIGNAME=VCO_GATE IS=0 .MODEL < model name> DINPUT [ model parameters] Table 2-17 Digital Input Model Parameters Model Description Parameters* CHI Capacitance to high level node CLO Capacitance to low level node FILE Digital input file name (Digital Files only) FORMAT Digital input file format (Digital Files only) S0NAME State “0” character abbreviation S0TSW State “0” switching time S0RLO State “0” resistance to low level node S0RHI State “0” resistance to high level node S1NAME State “1” character abbreviation S1TSW State “1” switching time S1RLO State “1” resistance to low level node S1RHI State “1” resistance to high level node S2NAME State “2” character abbreviation S2TSW State “2” switching time S2RLO State “2” resistance to low level node S2RHI State “2” resistance to high level node .. . S19NAME State “19” character abbreviation S19TSW State “19” switching time S19RLO State “19” resistance to low level node S19RHI State “19” resistance to high level node TIMESTEP Digital input file step-size (Digital Files only) * See .MODEL statement. Units Default farad farad 0 0 1 sec ohm ohm sec ohm ohm sec ohm ohm sec ohm ohm sec 1E-91 2-48 Analog Devices Note For more information on using the digital input device to simulate mixed analog/digital systems refer to your PSpice user’s guide. As shown in Figure 2-6, the digital input device is modeled as a time varying resistor from <low level node> to <interface node>, and another time varying resistor from <high level node> to <interface node>. Each of these resistors has an optional fixed value capacitor in parallel: CLO and CHI. When the state of the digital signal changes, the values of the resistors change (exponentially) from their present values to the values specified for the new state over the switching time specified by the new state. Normally the low and high level nodes would be attached to voltage sources which would correspond to the highest and lowest logic levels. (Using two resistors and two voltage levels, any voltage between the two levels can be created at any impedance. Figure 2-6 Digital Input Model N N Digital input 2-49 If SIGNAME = <digital signal name> is specified, this is the name of the digital signal in the input file which controls this digutal input device. Otherwise, the portion of the device name after the leading N identifies the name of the digital signal. If IS=<initial state name> is specified, then the initial state of the input (for the bias-point calculation, and TIME=0) is not the value specified by the input file (or the digital simulator) but the value specified by <initial state>. The digital input will remain in this state until a value is read, or received, which is different than the state at TIME=0. The value of < initial state> must be one of the state names (S0NAME through S19NAME) specified by the model. The state of the digital input may be viewed in Probe by specifying B(Nxxx). The value of B(Nxxx) is 0.0 if the current state is S0NAME, 1.0 if the current state is S1NAME, and so on through 19.0. For this reason it is convenient to use S0NAME for the lowest logic level, and S19NAME for the highest logic level. These values are not available for .PRINT or .PLOT output. If the file name Is DGTLPSPC, and the Parallel Analog/Digital Simulation option in included, then Pspice will obtain the digital input data from the digital simulator (for example, VIEWsimA/D). In this case the digital simulator must be running concurrently with Pspice, and they must both be simulating the same time interval. The format parameter is ignored if DGTLPSPC is specified for the file. Any number of digital input models may be specified. Different digital input models may reference the same file, or different files. (If the models reference the same file, the file must be specified in the same way, or unpredictable results will occur: for example, if the default drive is C:, then one model should not have FILE=C:TEST.DAT if another has FILE=TEST.DAT). 2-50 Analog Devices O Digital Output General Form Example O<name> <interface node> <reference node> <model name> + [DGTLNET = <digital I/O model name>] + [SIGNAME = <digital signal name>] OVCO 17 0 TO_TTL O5 22 100 TO_CMOS SIGNAME=VCO_OUT Table 2-18 Digital Output Model Parameters Model Parameters * Description Units Defaul t CHGONLY CLOAD 0: write each timestep, 1: write upon change 0 Output capacitor FILE Digital input file name (Digital Files only) FORMAT Digital input file format (Digital Files only) RLOAD Output resistor S0NAME State “0” character abbreviation S0VLO State “0” low level voltage volt S0VHI State “0” high level voltage volt S1NAME State “1” character abbreviation S1VLO State “1” low level voltage volt S1VHI State “1” high level voltage volt S2NAME State “2” character abbreviation S2VLO State “2” low level voltage volt S2VHI State “2” high level voltage volt . . S19NAME State “19” character abbreviation S19VLO State “19” low level voltage volt S19VHI State “19” high level voltage volt TIMESTEP Digital input file step-size sec TIMESCALE Scale factor for TIMESTEP (Digital Files only) • See .MODEL statement farad 0 1 ohm 1000 1E-9 1 O Digital Output 2-51 Note The digital output device is part of the mixed analog/digital simulation options for Pspice. For more information see the “Digital Files” chapter. As shown in Figure 2-7, the digital output device is modeled as a resistor and capacitor, of the values specified in the model statement, connected between <interface node> and <reference node>. At times which are integer multiples of TIMESTEP, the “state” of the device node is determined and written to the specified file. Figure 2-7 Digital Output Model The state of the node is determined by taking the difference in voltage between the <interface node> and the <reference node>, and comparing it (first) to the voltage range for the current state. If it is within the range, then the new state is the same as the old state. If it is not within the range for the current state, then the states are examined starting with S0NAME. The new state is the first one which contains the voltage within its range. (If none contain it, then the state is ‘?’ ). This allows the user to specify hysteresis for the state changes. If SIGNAME = <digital signal name> is specified, this is the name of the digital signal in the output file. Otherwise, the portion of the device name after the leading O identifies the name of the digital signal. 2-52 Analog Devices O The state of each device will be written to the output file at times which are integer multiples of TIMESTEP. The “time” which is written will be the integer time = TIMESCALE * TIME/TIMESTEP TIMESCALE defaults to 1, but if the digital simulator is using a very small timestep compared to the Pspice timestep, it can speed up the Pspice simulation to increase the value of both TIMESTEP and TIMESCALE. This is because Pspice must take time-steps no greater than the digital TIMESTEP size when a digital output is about to change, in order to accurately determine the exact time that the state changes. The value of TIMESTEP should therefore be the time resolution required at the analogdigital interface. The value of TIMESCALE is then used to adjust the output time to be in the same units as the digital simulator uses. For example, if you are doing a digital simulation with a timestep of 100ps, but your circuit has a clock rate of 1us, setting TIMESTEP to 0.1us should provide enough resolution. Setting TIMESCALE to 1000 will scale the output time to be in 100ps units. If CHGONLY=1 only those time-steps in which an digital output state changes are written to the file. The state of the digital output may be viewed in Probe by specifying B(Oxxx). The value of B(Oxxx) is 0.0 if the current state is S0NAME, 1.0 if the current state is S1NAME, and so on through 19.0. For this reason it is convenient to use S0NAME for the lowest logic level, and S19NAME for the highest logic level. These values are not available for .PRINT or .PLOT output. If the file name is PSPCDGTL, and the Parallel Analog/Digital Simulation option in included, then Pspice will obtain the digital input data from the digital simulator (for example, VIEWsimA/D ). In this case the digital simulator must be running concurrently with Pspice, and they must both be O Digital Output 2-53 simulating the same time interval. The format parameter is ignored if PSPCGTL is specified for the file. Any number of digital output models may be specified. Different digital input models may reference the same file, or different files. (If the models reference the same file, the file must be specified in the same way, or unpredictable results will occur: for example, if the default drive is C:, then one model should not have FILE=C:TEST.DAT if another has FILE=TEST.DAT). 2-54 Analog Devices Q Bipolar Transistor General Form Q<name> < collector node> <base node> <emitter node> + Examples [substrate node] <model name> [area value] Q1 14 2 13 PNPNOM Q13 15 3 0 1 NPNSTRONG 1.5 Q7 VC 5 12 [SUB] LATPNP Model Form .MODEL < model name> NPN [ model parameters] .MODEL < model name> PNP [ model parameters] .MODEL < model name> LPNP [ model parameters] Figure 2-8 Bipolar Transistor Model (enhanced Gummel-Poon) As shown, the bipolar transistor is modeled as an intrinsic transistor using ohmic resistances in series with the collector (RC/area), the base (value varies with current, see equations below), and with the emitter (RE/area). Positive current is current flowing into a terminal. The [area value] is the relative device area and defaults to 1. For those model parameters which have alternate names, such as VAF and VA (the alternate name is shown by using parentheses), either name can be used. Q Bipolar Transistor 2-55 The substrate node is optional, and if not specified it defaults to ground. Because the simulator allows alphanumeric names for nodes, and because there is no easy way to distinguish these from the model names, it makes it necessary to enclose the name (not a number) used for the substrate node using square brackets “[ ]”. Otherwise it is interpreted as a model name. See the third example. For model types NPN and PNP, the isolation junction capacitance is connected between the intrinsic-collector and substrate nodes. This is the same as in SPICE2, or SPICE3, and works well for vertical IC transistor structures. For lateral IC transistor structures there is a third model, LPNP, where the isolation junction capacitance is connected between the intrinsic-base and substrate nodes. Table 2-19 Bipolar Transistor Model Parameters Model Description Parameters Units Default AF Flicker noise exponent BF Ideal maximum forward beta 100 BR Ideal maximum reverse beta 1 CJC Base-collector zero-bias p-n capacitance farad 0 CJE Base-emitter zero-bias p-n capacitance farad 0 Substrate zero-bias p-n capacitance farad 0 CJS(CCS) 1 EG Bandgap voltage (barrier height) eV 1.11 FC Forward-bias depletion capacitor coefficient IKF (IK) Corner for forward-beta high-current roll-off amp infinite IKR Corner for reverse-beta high-current roll-off amp infinite IRB Current at which Rb falls halfway to RBM amp infinite IS Transport saturation current amp 1E-16 ISC (C4) Base-collector leakage saturation current amp 0 ISE (C2) Base-emitter leakage saturation current amp 0 ISS Substrate p-n saturation current amp 0 ITF Transit time dependency on Ic amp 0 KF Flicker noise coefficient MJC (MC) Base-collector p-n grading factor 0.33 MJE (ME) Base-emitter p-n grading factor 0.33 MJS (MS) Substrate p-n grading factor 0 NC Base-collector leakage emission coefficient 2 0.5 0 2-56 Analog Devices Q Table 2-19 Bipolar Transistor Model Parameters (continued) Model Parameters Description Units Default NE Base-emitter leakage emission coefficient 1.5 NF Forward current emission coefficient 1 NR Reverse current emission coefficient 1 NS Substrate p-n emission coefficient 1 PTF Excess phase @ 1/(2p·TF)Hz degree 0 QCO Epitaxial region charge factor coulomb 0 RB Zero-bias (maximum) base resistance ohm 0 RBM Minimum base resistance ohm RB RC Collector ohmic resistance ohm 0 RE Emitter ohmic resistance ohm 0 TF Ideal forward transit time sec 0 TR Ideal reverse transit time sec 0 -1 0 -2 0 -1 0 -2 0 -1 0 -2 0 -1 0 -2 0 TRB1 RB temperature coefficient (linear) °C TRB2 RB temperature coefficient (quadratic) °C TRC1 RC temperature coefficient (linear) °C TRC2 RC temperature coefficient (quadratic) °C TRE1 RE temperature coefficient (linear) °C TRE2 RE temperature coefficient (quadratic) °C TRM1 RBM temperature coefficient (linear) °C TRM2 RBM temperature coefficient (quadratic) °C VAF (VA) Forward Early voltage volt infinite VAR (VB) Reverse Early voltage volt infinite VJC (PC) Base-collector built-in potential volt 0.75 VJE (PE) Base-emitter built-in potential volt 0.75 VJS (PS) Substrate p-n built-in potential volt 0.75 VTF Transit time dependency on Vbc volt infinite XCJC Fraction of CJC connec. internally to Rb 1 XTB Forward and reverse beta temp coeff. 0 XTF Transit time bias dependence coefficient 0 XTI (PT) IS temperature effect exponent 3 Q Bipolar Transistor 2-57 The parameters ISE (C2) and ISC (C4) can be set to be greater than one. In this case, they are interpreted as multipliers of IS instead of absolute currents: that is, if ISE is greater than one then it is replaced by ISE·IS. Likewise for ISC. Equations In the following equations: Vbe = intrinsic base-intrinsic emitter voltage Vbc = intrinsic base-intrinsic collector voltage Vbs = intrinsic base-substrate voltage Vbx = extrinsic base-intrinsic collector voltage Vce = intrinsic collector-intrinsic emitter voltage Vjs = (NPN) intrinsic collector-substrate voltage = (PNP) intrinsic substrate-collector voltage = (LPNP) intrinsic base-substrate voltage Vt = k·T/q (thermal voltage) k = Boltzmann’s constant q = electron charge T = analysis temperature (°K) Tnom = nominal temperature (set using TNOM option) Other variables are from the model parameter list. These equations describe an NPN transistor. For the PNP and LPNP devices, reverse the signs of all voltages and currents. DC Currents Note: Positive current is current flowing into a terminal. Ib = base current = area·(Ibe1/BF + Ibe2 + Ibc1/BR + Ibc2) Ic = collector current = area·(Ibe1/Kqb - Ibc1/Kqb - Ibc1/BR - Ibc2) Vbe/(NF·Vt) Ibe1 = forward diffusion current = IS·(e -1) Vbe/(NE·Vt) Ibe2 = non-ideal base-emitter current = ISE·(e -1) Vbc/(NR·Vt) Ibc1 = reverse diffusion current = IS·(e -1) Vbc/(NC·Vt) Ibc2 = non-ideal base-collector current = ISC·(e -1) 1/2 Kqb = base charge factor = Kq1·(1+(1+4·Kq2) )/2 Kq1 = 1/(1 - Vbc/VAF - Vbe/VAR) Kq2 = Ibe1/IKF + Ibc1/IKR Is = substrate current = area·ISS·(e Vjs/(NS·Vt) -1) Rb = actual base parasitic resistance For: IRB = infinite (default value) Rb = (RBM + (RB-RBM)/Kqb)/area For: IRB > 0 2 Rb = (RBM + 3·(RB-RBM)·(tan(x)-x)/(x·tan (x)))/area 2 1/2 where x = ((1+(144/ π )·Ib/(area·IRB)) 2 1/2 -1)/ ((24/ π ) ·(Ib/(area· IRB)) ) 2-58 Analog Devices Q Capacitances Note: All capacitances, except Cbx, are between terminals of the intrinsic transistor which is inside of the col-lector, base, and emitter parasitic resistances. Cbx is between the intrinsic collector and the extrinsic base. Cbe = base-emitter capacitance = area·(Ctbe + Cjbe) Ctbe = transit time capacitance = tf·Gbe 2 3 tf = effective TF= TF·(1+XTF·(3x -2x ) ·e Vbc/(1.44·VTF) ) where x= Ibe1/(Ibe1+area·ITF) Gbe = DC base-emitter conductance = (dIbe1)/(dVbe) For: Vbe ≤ FC·VJE Cjbe = CJE·(1-Vbe/VJE) -MJE For: Vbe > FC·VJE Cjbe = CJE·(1-FC) -(1+MJE) ·(1-FC·(1+MJE)+MJE·Vbe/VJE) Cbc = base-collector capacitance = area·(Ctbc+XCJC·Cjbc) Ctbc = transit time capacitance = TR·Gbc Gbc = DC base-collector conductance = (dIbc)/(dVbc) For: Vbc ≤ FC·VJC Cjbc = CJC·(1-Vbc/VJC) -MJC For: Vbc > FC·VJC Cjbc = CJC·(1-FC) -(1+MJC) ·(1-FC·(1+MJC)+MJC·Vbc/VJC) Cbx = extrinsic-base to intrinsic-collector capacitance = area·(1-XCJC)·Cjbx For: Vbx ≤ FC·VJC Cjbx = CJC·(1-Vbx/VJC) -MJC For: Vbx > FC·VJC Cjbx = CJC·(1-FC) -(1+MJC) ·(1-FC·(1+MJC)+MJC·Vbx/VJC) Cjs = substrate junction capacitance = area·Cjjs For: Vjs ≤ 0 Cjjs = CJS·(1-Vjs/VJS) -MJS For: Vjs > 0 Cjjs = CJS·(1+MJS·Vjs/VJS) (assumes FC = 0) Q Bipolar Transistor 2-59 Temperature Effects IS(T) (T/Tnom-1)·EG/(N·Vt) = IS·e ·(T/Tnom) XTI/N where N = 1 XTB )·e (T/Tnom-1)·EG/(NE·Vt) XTB )·e (T/Tnom-1)·EG/(NC·Vt) ·(T/Tnom) XTB )·e (T/Tnom-1)·EG/(NS·Vt) ·(T/Tnom) ISE(T) = (ISE/(T/Tnom) ISC(T) = (ISC/(T/Tnom) ISS(T) = (ISS/(T/Tnom) BF(T) = BF·(T/Tnom) BR(T) = BR·(T/Tnom) RE(T) = RE·(1+TRE1·(T-Tnom)+TRE2·(T-Tnom) ) RB(T) = RB·(1+TRB1·(T-Tnom)+TRB2·(T-Tnom) ) XTI/NE XTI/NC XTI/NS XTB XTB 2 2 RBM(T) RC(T) ·(T/Tnom) 2 = RBM·(1+TRM1·(T-Tnom)+TRM2·(T-Tnom) ) 2 = RC·(1+TRC1·(T-Tnom)+TRC2·(T-Tnom) ) VJE(T) = VJE·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) VJC(T) = VJC·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) VJS(T) = VJS·T/Tnom - 3·Vt·ln(T/Tnom) - Eg(Tnom)·T/Tnom + Eg(T) 2 where Eg(T) = silicon bandgap energy = 1.16 - .000702·T /(T+1108) CJE(T) = CJE·(1+MJE·(.0004·(T-Tnom)+(1-VJE(T)/VJE))) CJC(T) = CJC·(1+MJC·(.0004·(T-Tnom)+(1-VJC(T)/VJC))) CJS(T) = CJS·(1+MJS·(.0004·(T-Tnom)+(1-VJS(T)/VJS))) The collector, base, and emitter parasitic resistances have no temperature dependence. 2-60 Analog Devices Q Noise Noise is calculated assuming a one hertz bandwidth, using the following spectral power densities (per unit bandwidth): the parasitic resistances generate thermal noise ... 2 Ic = 4·k·T/(RC/area) 2 Ib = 4·k·T/Rb 2 Ie = 4·k·T/(RE/area) the base and collector currents generate shot and flicker noise ... 2 AF 2 AF Ib = 2·q·Ib + KF·Ib Ic = 2·q·Ic + KF·Ic /FREQUENCY /FREQUENCY References For a more complete description of bipolar transistor models, refer to [1] Ian Getreu, Modeling the Bipolar Transistor, Tektronix, Inc. part# 062-2841-00. R Resistor 2-61 Resistor General Form R<name> <(+) node> <(-) node> [model name] <value> Examples RLOAD 15 0 2K 1 2 2.4E4 R2 Model Form .MODEL < model name> RES [ model parameters] (+) and (-) nodes Define the polarity when the resistor has a positive voltage across it. Positive current flows from the (+) node through the resistor to the (-) node. [model name] If this is included and TCE (in the model) is not specified, then the resistance is given by the formula 2 <value>·R·(1+TC1·(T-Tnom)+TC2·(T-Tnom) ) where <value> is normally positive (though it can be negative, but not zero). If [model name] is included and TCE (in the model) is specified, then the resistance is given by the formula <value>·R·1.01 TCE·(T-Tnom) where <value> is normally positive (though it can be negative, but not zero). “Tnom” is the nominal temperature (set using TNOM option).R Table 2-20 Resistor Model Parameters Model Description Parameters R Resistance multiplier Units Default TC1 Linear temperature coefficient °C -1 0 TC2 Quadratic temperature coefficient °C -2 0 TCE Exponential temperature coefficient %/°C 0 1 Noise Noise is calculated assuming a one hertz bandwidth. The resistor generates thermal noise using the following spectral power density (per unit bandwidth) 2 i = 4·k·T/resistance 2-62 Analog Devices S Voltage-Controlled Switch General Form S<name> + + <(+) switch node> <(-) switch node> <(+) controlling node> <(-) controlling node> <model name> Examples S12 13 17 2 0 SMOD SESET 5 0 15 3 RELAY Model Form .MODEL < model name> VSWITCH [ model parameters] The voltage-controlled switch is a special kind of voltage-controlled resistor. The resistance between the <(+) switch node> and <(-) switch node> depends on the voltage between the <(+) controlling node> and <(–) controlling node>. The resistance varies continuously between the RON and ROFF model parameters. A resistance of 1/GMIN is connected between the controlling nodes to keep them from floating. See the .OPTIONS statement (page 1-26) for setting GMIN. We have chosen this model for a switch to try to minimize numerical problems. However, there are a few things to keep in mind: With double precision numbers Pspice can handle only a dynamic range of about 12 decades. So, we do not recommend making the ratio of ROFF to RON greater than 1E+12. Similary, we do not recommend making the transition region too narrow. Remember that in the transition region the switch has gain. The narrower the region, the higher the gain and the greater the potential for numerical problems. Although very little computer time is required to evaluate switches, during transient analysis the simulator must step through the transition region using a fine enough step size to get an accurate waveform. Applying many transitions can produce long run times when evaluating the other devices in the circuit at each time step. RON and ROFF must be greater than zero and less than 1/GMIN. S Voltage-Controlled Switch 2-63 Table 2-21 Voltage-Controlled Switch Model Parameters Model Parameters ROFF Description Units Default “Off” resistance ohm 1E+6 RON “On” resistance ohm 1.0 VOFF Control voltage for “off” state volt 0.0 VON Control voltage for “on” state S volt 1.0 Equations In the following equations: Vc Lm Lr Vm Vd k T = voltage across control nodes 1/2 = log-mean of resistor values = ln((RON·ROFF) ) = log-ratio of resistor values = ln(RON/ROFF) = mean of control voltages = (VON+VOFF)/2 = difference of control voltages = VON-VOFF = Boltzmann’s constant = analysis temperature (°K) Switch Resistance Rs = switch resistance If: VON > VOFF For: Vc ≥ VON Rs = RON For: Vc ≤ VOFF Rs = ROFF For: VOFF < Vc < VON 3 3 Rs = exp(Lm + 3·Lr·(Vc-Vm)/(2·Vd) - 2·Lr·(Vc-Vm) /Vd ) If: VON < VOFF For: Vc ≤ VON Rs = RON For: Vc ≥ VOFF Rs = ROFF For: VOFF > Vc > VON 3 3 Rs = exp(Lm - 3·Lr·(Vc-Vm)/(2·Vd) + 2·Lr·(Vc-Vm) /Vd ) Noise Noise is calculated assuming a one hertz bandwidth. The voltage-controlled switch generates thermal noise as if it were a resistor having the same resistance that the switch has at the bias point, using the following spectral power density (per unit bandwidth) 2 i = 4·k·T/Rs 2-64 Analog Devices T Transmission Line General Form T<name> + + Examples T1 1 2 3 4 Z0=220 TD=115ns T2 1 2 3 4 Z0=220 F=2.25MEG T3 1 2 3 4 Z0=220 F=4.5MEG NL=0.5 Model Form .MODEL < model name> TRN [ model parameters] <A port (+) node> <A port (-) node> <B port (-) node> <B port (+) node> Z0=<value> [TD=<value>] [F=<value> [NL=<value>]] Figure 2-9 Transmission Line Model T Table 2-22 Transmission Line Model Parameters Model Parameters ZO Description Units Default Characteristic impedance ohms none TD Transmission delay seconds none F Frequency for NL Hz none NL Relative wavelength none .25 As shown in Figure 2-22, the transmission line device is a bidirectional, delay line. It has two ports, A and B. The (+) and (-) nodes define the polarity of a positive voltage at a port. In Figure 2-12, port A’s (+) and (-) nodes are one and two, and port B’s (+) and (-) nodes are three and four, respectively. T Transmission Line 2-65 Z0 is the characteristic impedance. The transmission line’s length can be specified either by TD, a delay in seconds, or by F and NL, a frequency and a relative wavelength at F. NL defaults to 0.25 (F is then the quarter-wave frequency). Although TD and F are both shown as optional, one of the two must be specified. Examples T1, T2, and T3 all specify the same transmission line. Note Both Z0 (“zee-zero”) and ZO (“zee-oh”) are accepted by the simulator. During transient (.TRAN) analysis, the internal time step is limited to be no more than one-half the smallest transmission delay, so short transmission lines cause long run times. 2-66 Analog Devices U Digital Device General Form Examples U<name> <type> ([parameter value]) <node> + [timing model name] <IO model name> U<name> STIM (<width value>,<format value>) <node> + <IO model name> [TIMESTEP=<stepsize value>] + <waveform description> U1 NAND(2) 1 2 U2 JKFF(1) 3 5 10 DO_GATE IO_DFT 200 3 3 10 2 U3 STIM(1,1) 110 + 0nS, 1 + 40nS, 0 D_293ASTD IO_STD STMIOMDL TIMESTEP=10NS Table 2-23 Digital Device Model Parameters Model Description Units Default INLD Input load capacitance farad 0 OUTLD Output load capacitance farad 0 DRVH Output high level resistance ohm 0 DRVL Output low level resistance ohm 0 AtoD Name of AtoD subcircuit none DtoA Name of DtoA subcircuit none Parameters Note The digital devices are part of the Digital Simulation option for Pspice. For more information on these devices see the “Digital Simulation” chapter. W Current-Controlled Switch 2-67 Current-Controlled Switch General Form W<name> + <(+) switch node> <(-) switch node> <controlling V device name> <model name> Examples W12 13 17 WRESET 5 0 Model Form .MODEL < model name> ISWITCH [ model parameters] VC WMOD VRESET RELAY Table 2-24 Current-Controlled Switch Model Parameters Model Parameters Description Units Default IOFF Control current for “off” state amp 0.0 ION Control current for “on” state amp 1E-3 ROFF “Off” resistance ohm 1E+6 RON “On” resistance W ohm 1.0 The current-controlled switch is a special kind of current-controlled resistor. <controlling V device name> The resistance between the <(+) switch node and <(-) switch node> depends on the current through <controlling V device name>. The resistance varies continuously between RON and ROFF. RON and ROFF Must be greater than zero and less than 1/GMIN. A resistance of 1/GMIN is connected between the controlling nodes to keep them from floating. See the .OPTIONS statement (page 1-26) for setting GMIN. 2-68 Analog Devices W This model was chosen for a switch to try to minimize numerical problems. However, there are a few things that must be evaluated: Using double precision numbers, the simulator can handle only a dynamic range of about 12 decades. Therefore, it is not recommended making the ratio of ROFF to RON greater than 1E+12. Similarly, it is also not recommended making the transition region too narrow. Remembering that in the transition region the switch has gain. The narrower the region, the higher the gain and the greater the potential for numerical problems. Although very little computer time is required to evaluate switches, during transient analysis the simulator must step through the transition region using a fine enough step size to get an accurate waveform. Having many transitions can produce long run times when evaluating the other devices in the circuit for many times. In the following equations: Ic = controlling current Lm = log-mean of resistor values = ln((RON·ROFF) Lr = log-ratio of resistor values = ln(RON/ROFF) Im = mean of control currents = (ION+IOFF)/2 Id = difference of control currents = ION-IOFF k = Boltzmann’s constant T = analysis temperature (°K) 1/2 ) W Current-Controlled Switch 2-69 Switch Resistance Rs = switch resistance If: ION > IOFF For: Ic ≥ ION Rs = RON For: Ic ≤ IOFF Rs = ROFF For: IOFF < Ic < ION 3 3 3 3 Rs = exp(Lm + 3·Lr·(Ic-Im)/(2·Id) - 2·Lr·(Ic-Im) /Id ) If: ION < IOFF For: Ic ≤ ION Rs = RON For: Ic ≥ IOFF Rs = ROFF For: IOFF > Ic > ION Rs = exp(Lm - 3·Lr·(Ic-Im)/(2·Id) + 2·Lr·(Ic-Im) /Id ) Noise Noise is calculated assuming a one hertz bandwidth. The current-controlled switch generates thermal noise as if it were a resistor using the same resistance as the switch has at the bias point, using the following spectral power density (per unit bandwidth) 2 i = 4·k·T/Rs 2-70 Analog Devices X Subcircuit Instantiation General Form X<name> [node]* Examples X12 <subcircuit name> 100 101 200 201 DIFFAMP XBUFF 13 15 UNITAMP <subcircuit name> The <subcircuit name> is the name of the subcircuit’s definition (see .SUBCKT statement). There must be the same number of nodes in the call as in the subcircuit’s definition. This statement causes the referenced subcircuit to be inserted into the circuit using the given nodes to replace the argument nodes in the definition. It allows a block of circuitry to be defined once and then used in several places. Subcircuit references can be nested. That is, a call can be given to subcircuit A, whose definition contains a call to subcircuit B. The nesting can be to any level, but must not be circular: for example, if subcircuit A’s definition contains a call to subcircuit B, then subcircuit B’s definition must not contain a call to subcircuit A.