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Low-Power Design and Test Introduction Vishwani D. Agrawal Srivaths Ravi Auburn University, USA Texas Instruments India [email protected] [email protected] Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 1 Acknowledgments The lecturers wish to thank Synopsys (India) and Sequence Design (India) for their help in preparation of demos for this course. Special thanks to Anantha Bhat [[email protected]] Bhavesh Shah [[email protected]] Visit http://www.synopsys.com/ for more information Rahul Prasad [[email protected]] Visit http://www.sequencedesign.com/ for more information Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 2 Course Objective Low-power is a current need in VLSI design. Learn basic ideas, concepts and methods. Gain experience with CAD tools. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 3 Course Schedule Day 1, Monday, July 30, 2007 9 – 10:30AM 10:30 – 11AM 11 – 12:30PM 12:30 – 2PM 2 – 3:30PM 3:30 – 4PM 4 – 5:30PM Lecture 1 Introduction (30*) VA Lecture 2 Dynamic and static power in CMOS (39) VA (56) VA (55) SR Lecture 5 Gate-level power optimization (45) VA Lecture 6 Memory and multicore design (40) VA Lecture 7 High-level power reduction and management (50) SR Lecture 8 Test power (35) SR Coffee break Lunch Lecture 3 Logic-level power estimation Coffee break Lecture 4 High-level power analysis Day 2, Tuesday, July 31, 2007 9 – 10:30AM 10:30 – 11AM 11 – 12:30PM 12:30 – 2PM 2 – 3:30PM 3:30 – 4PM 4 – 5:30PM Coffee break Lunch Coffee break * Number of slides Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 4 Introduction Power Consumption of VLSI Chips Why is it a concern? Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 5 ISSCC, Feb. 2001, Keynote “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. Patrick P. Gelsinger Senior Vice President General Manager Digital Enterprise Group INTEL CORP. Copyright Agrawal & Srivaths, 2007 “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .” Low-Power Design and Test, Lecture 1 6 VLSI Chip Power Density Sun’s Surface Power Density (W/cm2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 Hot Plate 10 4004 8008 8085 386 286 8080 1 1970 Copyright Agrawal & Srivaths, 2007 1980 P6 Pentium® 486 1990 Year Source: Intel 2000 Low-Power Design and Test, Lecture 1 2010 7 SIA Roadmap for Processors (1999) Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic transistors/cm2 6.2M 18M 39M 84M 180M 390M Clock (GHz) 1.25 2.1 3.5 6.0 10.0 16.9 Chip size (mm2) 340 430 520 620 750 900 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf. Power (W) 90 130 160 170 175 183 Source: http://www.semichips.org Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 8 Recent Data Source: http://www.eetimes.com/story/OEG20040123S0041 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 9 Low-Power Design Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. Low-power design methods: Algorithms and architectures High-level and software techniques Gate and circuit-level methods Test power Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 10 VLSI Building Blocks Finite-state machine (FMS) Bus Flip-flops and shift registers Memories Datapath Processors Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 11 State Encoding for a Counter Two-bit binary counter: State sequence, 00 → 01 → 10 → 11 → 00 Six bit transitions in four clock cycles 6/4 = 1.5 transitions per clock Two-bit Gray-code counter State sequence, 00 → 01 → 11 → 10 → 00 Four bit transitions in four clock cycles 4/4 = 1.0 transition per clock Gray-code counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston: Kluwer Academic Publishers (now Springer), 1998. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 12 Binary Counter: Original Encoding Present state a 0 0 1 1 Next state b 0 1 0 1 A = a’b + ab’ B = a’b’ + ab’ Copyright Agrawal & Srivaths, 2007 a A b A 0 1 1 0 B 1 0 1 0 B CK CLR Low-Power Design and Test, Lecture 1 13 Binary Counter: Gray Encoding Present state a 0 0 1 1 Next state b 0 1 0 1 A = a’b + ab B = a’b’ + a’b Copyright Agrawal & Srivaths, 2007 a A A 0 1 0 1 B 1 1 0 0 B b CK CLR Low-Power Design and Test, Lecture 1 14 Three-Bit Counters State Binary No. of toggles Gray-code State No. of toggles 000 - 000 - 001 1 001 1 010 2 011 1 011 1 010 1 100 3 110 1 101 1 111 1 110 2 101 1 111 1 100 1 000 3 000 1 Av. Transitions/clock = 1.75 Copyright Agrawal & Srivaths, 2007 Av. Transitions/clock = 1 Low-Power Design and Test, Lecture 1 15 N-Bit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2N – 1) Gray-code counter: T(gray) = 2N T(gray)/T(binary) = 2N-1/(2N – 1) → 0.5 Bits T(binary) T(gray) T(gray)/T(binary) 1 2 2 1.0 2 6 4 0.6667 3 14 8 0.5714 4 30 16 0.5333 5 62 32 0.5161 6 126 64 0.5079 ∞ - - 0.5000 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 16 FSM State Encoding Transition probability based on PI statistics 0.6 0.6 11 0.3 0.4 00 0.6 0.1 01 0.3 0.1 0.4 01 00 0.9 0.6 0.1 0.1 11 0.9 Expected number of state-bit transitions: 2(0.3+0.4) + 1(0.1+0.1) = 1.6 1(0.3+0.4+0.1) + 2(0.1) = 1.0 State encoding can be selected using a power-based cost function. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 17 FSM: Clock-Gating Moore machine: Outputs depend only on the state variables. If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. Xi/Zk Si Sk Sj Copyright Agrawal & Srivaths, 2007 Xj/Zk Xk/Zk Clock can be stopped when (Xk, Sk) combination occurs. Low-Power Design and Test, Lecture 1 18 Clock-Gating in Moore FSM Flip-flops PI Clock activation logic CK Copyright Agrawal & Srivaths, 2007 Latch Combinational logic PO L. Benini and G. De Micheli, Dynamic Power Management, Boston: Springer, 1998. Low-Power Design and Test, Lecture 1 19 Bus Encoding for Reduced Power Example: Four bit bus 0000 → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → 0001 will have only one transition. Number of bit transitions after inversion encoding Bit-inversion encoding for N-bit bus: Copyright Agrawal & Srivaths, 2007 N N/2 0 0 N/2 Number of bit transitions Low-Power Design and Test, Lecture 1 N 20 Sent data Received data Bus-Inversion Encoding Logic Polarity decision logic Copyright Agrawal & Srivaths, 2007 Bus register Polarity bit M. Stan and W. Burleson, “Bus-Invert Coding for Low Power I/O,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 49-58, March 1995. Low-Power Design and Test, Lecture 1 21 Clock-Gating in Low-Power Flip-Flop D D Q CK Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 22 Reduced-Power Shift Register D Q D Q D Q D Q multiplexer D D Q D Q D Q D Output Q CK(f/2) Flip-flops are operated at full voltage and half the clock frequency. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 23 Power Consumption of Shift Register P = C’VDD2f/n 16-bit shift register, 2μ CMOS Deg. Of parallelism Freq (MHz) Power (μW) 1 33.0 1535 2 16.5 887 4 8.25 738 C. Piguet, “Circuit and Logic Level Design,” pages 103-133 in W. Nebel and J. Mermet (ed.), Low Power Design in Deep Submicron Electronics, Springer, 1997. Copyright Agrawal & Srivaths, 2007 Normalized power 1.0 0.5 0.25 0.0 1 Low-Power Design and Test, Lecture 1 2 4 Degree of parallelism, n 24 Books on Low-Power Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and CAD Tools, Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, New York: IEEE Press, 1998. J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels using Formal Methods, Boston: Springer, 1999. M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Boston: Springer, 1997. R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum Publishers, 2002. S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston: Springer, 1998. J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI Circuits, New York: WileyInterscience, 1999. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Boston: Springer, 1997. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Boston: Springer, 2005. W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics, Boston: Springer, 1997. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 25 Books on Low-Power Design (2) N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, 2005. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston: Springer, 2002. C. Piguet, Low-Power Electronics Design, Boca Raton: Florida: CRC Press, 2005. J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston: Springer, 1996. S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor Networks, Boston: Springer, 2003. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design, New York: Wiley-Interscience, 2000. E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE Press, 1999. W. A. Serdijn, Low-Voltage Low-Power Analog Integrated Circuits, Boston:Springer, 1995. S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Wideband CDMA System Design, Boston: Springer, 1998. G. Verghese and J. M. Rabaey, Low-Energy FPGAs, Boston: springer, 2001. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998. K.-S. Yeo and K. Roy, Low-Voltage Low-Power Subsystems, McGraw Hill, 2004. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 26 Other Books Useful in Low-Power Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of HighPerformance Microprocessor Circuits, New York: IEEE Press, 2001. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Reading, Massachusetts, Addison-Wesley, 2005. S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, New York: McGraw-Hill, 1996. E. Larsson, Introduction to Advanced System-on-Chip Test Design and Optimization, Springer, 2005. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Prentice-Hall, 2003. J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, New York: IEEE Press, 2004. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 27 Problem: Bus Encoding A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial. Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224-225. [Hint: You should be able to solve this problem without the help of the reference.] Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 28 Solution: Bus Encoding Un-coded bus: Two consecutive bits can be 00, 01, 10 and 11, each with a probability 0.25. Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2n/4. Encoded bus: Encoded bus contains 2n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2–n, and CV 2 with probability 1 – 2–n. The average per pattern energy for the 1-hot encoded bus is CV 2(1 – 2–n). Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 29 Solution: Bus Encoding (Cont.) Power ratio = Encoded bus power / un-coded bus power = 4(1 – 2–n)/n → 4/n for large n For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2–n)/n ≤ 1, or 1 – 2–n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4. The following table shows 1-hot encoded bus power ratio as a function of bus width: n 4(1 – 2–n)/n n 4(1 – 2–n)/n 1 2.0000 8 0.4981 2 1.5000 16 0.2500 = 1/4 3 1.1670 32 1/8 4 0.9375 64 1/16 Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 1 30