OPA445 High Voltage FET-Input FEATURES DESCRIPTION

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OPA445
SBOS156B − MARCH 1987 − REVISED APRIL 2008
High Voltage FET-Input
OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
D WIDE-POWER SUPPLY RANGE:
D
D
D
±10V to ±45V
HIGH SLEW RATE: 15V/µs
LOW INPUT BIAS CURRENT: 10pA
STANDARD-PINOUT TO-99, DIP, SO-8
PowerPAD, AND SO-8 SURFACE-MOUNT
PACKAGES
APPLICATIONS
D
D
D
D
D
D
D
TEST EQUIPMENT
HIGH-VOLTAGE REGULATORS
POWER AMPLIFIERS
DATA ACQUISITION
SIGNAL CONDITIONING
AUDIO
PIEZO DRIVERS
The OPA445 is a monolithic operational amplifier capable
of operation from power supplies up to ±45V and output
currents of 15mA. It is useful in a wide variety of
applications requiring high output voltage or large
common-mode voltage swings.
The OPA445’s high slew rate provides wide powerbandwidth response, which is often required for
high-voltage applications. FET input circuitry allows the
use of high-impedance feedback networks, thus minimizing their output loading effects. Laser trimming of the input
circuitry yields low input offset voltage and drift.
The OPA445 is available in standard pinout TO-99, DIP-8,
and SO-8 surface-mount packages as well as an SO-8
PowerPAD package for reducing junction temperature. It
is fully specified from −25°C to +85°C and operates from
−55°C to +125°C. A SPICE macromodel is available for
design analysis (from www.ti.com).
OPA445
OPA445
NC
Offset
Trim
−In
8
7 V+
1
2
+In
6 Output
3
4
5 Offset
Trim
Offset Trim
1
8
NC
−In
2
7
V+
+In
3
6
Output
V−
4
5
Offset Trim
DIP−8, SO−8, SO−8 PowerPAD
V−
NC = No internal connection;
leave NC floating or connect to GND, V+, or V−.
Case is connected to V−
TO−99
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners.
www.BDTIC.com/TI
Copyright  1987−2008, Texas Instruments Incorporated
! ! www.ti.com
""#
www.ti.com
SBOS156B − MARCH 1987 − REVISED APRIL 2008
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |±VS| − 3V
Storage Temperature Range: M . . . . . . . . . . . . . . −65°C to +150°C
P, U, DDA . . . . . . . −55°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C
Output Short-Circuit to Ground (TJ < +125°C) . . . . . . Continuous
Junction Temperature: M . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Junction Temperature: P, U, DDA . . . . . . . . . . . . . . . . . . . . . +150°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
OPA445AP
DIP-8
P
OPA445AP
OPA445AU
SO-8 Surface-Mount
D
OPA445AU
OPA445ADDA
SO-8 PowerPAD
DDA
OPA445
OPA445BM
TO-99 8-Pin
LMC
OPA445BM
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
2
www.BDTIC.com/TI
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −25°C to +85°C. VS = ±40V.
At TA = +25°C, VS = ±40V, and RL = 5kΩ, unless otherwise noted.
OPA445BM
MAX
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
vs Power Supply
VCM = 0, IO = 0
TA = −25°C to +85°C
VS = ±10V to ±45V
±1
±10
4
±3
IB
VCM = 0V
±10
IOS
VCM = 0V
±4
TEST CONDITIONS
VOS
VOS/dT
PSRR
INPUT BIAS CURRENT(1)
Input Bias Current
Over Specified Temperature Range
Input Offset Current
Over Specified Temperature Range
NOISE
Input Voltage Noise Density, f = 1kHz
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection
Over Specified Temperature Range
MIN
en
in
VCM
CMRR
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
Full Power Bandwidth
Rise Time
Overshoot
Total Harmonic Distortion + Noise
OUTPUT
Voltage Output
Over Specified Temperature Range
Current Output
Output Resistance, Open Loop
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Specified Operating Range
Operating Voltage Range
Quiescent Current
AOL
GBW
SR
THD+N
VS = ±40V
VCM = −35V to +35V
100
97
VO = 70VPP
VO = 70VPP
VO = ±200mV
G = +1, ZL = 5kΩ || 50pF
f = 1kHz, VO = 3.5Vrms, G = 1
f = 1kHz, VO = 10Vrms, G = 1
5
23
VO = ±28V
dc
CLOAD
IQ
110
∗
∗
2
15
70
100
35
0.0002
0.00008
qJA
Thermal Resistance, Junction-to-Case
qJC
∗
∗
(V+) − 5
(V+) − 5
∗
*
∗
220
±26
See Typical Characteristic(2)
±40
±4.2
−25
−55
−65
±1.5
±5
∗
mV
µV/°C
µV/V
±100
±20
±40
±10
pA
nA
pA
nA
∗
∗
∗
∗
IO = 0
UNITS
∗
1013 || 1
1014 || 3
±10
MAX
∗
±50
±10
±20
±5
∗
∗
*
VS
TEMPERATURE RANGE
Specification Range
Operating Range
Storage Range
Thermal Resistance,
Junction-to-Ambient
TO-99
DIP-8
SO-8 Surface-Mount
SO-8 PowerPAD(3)
100
(V+) − 5
(V−) + 5
(V−) + 5
±15
TYP
*
∗
95
(V−) + 5
80
80
VO = −35V to +35V
VO
IO
RO
ISC
MIN
15
6
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
Over Specified Temperature Range
OPA445AP, AU, ADDA
TYP
PARAMETER
∗
nV/√Hz
fA/√Hz
∗
Ω || pF
Ω || pF
∗
dB
dB
∗
∗
∗
∗
∗
∗
∗
MHz
V/µs
kHz
ns
%
%
%
∗
*
∗
∗
∗
∗
±45
±4.7
∗
+85
+125
+125
∗
∗
∗
∗
−55
+125
∗
∗
∗
V
V
mA
Ω
mA
V
V
mA
°C
°C
°C
100
150
52
°C/W
°C/W
°C/W
°C/W
10
°C/W
200
SO-8 PowerPAD(3)
V
dB
dB
NOTE: ∗ Specifications same as OPA445BM.
(1) High-speed test at TJ = +25°C.
(2) See Small-Signal Overshoot vs Load Capacitance in the Typical Characteristics section.
(3) Test board 1in x 0.5in heat-spreader, 1oz copper.
www.BDTIC.com/TI
3
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
At TA = +25°C and VS = ±40V, unless otherwise noted.
OPEN−LOOP GAIN AND PHASE
vs FREQUENCY
OPEN−LOOP GAIN AND SUPPLY CURRENT
vs SUPPLY VOLTAGE
140
125
−45
80
−90
θ
60
Phase (_ )
−135
40
115
AVOL
110
105
Gain
20
−185
100
1k
10k
3.5
100
0
10
100k
1M
3.0
95
10
10M
20
GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE
50
2.2
16
19
14
2.2
13
2.0
GBW
12
1.8
Slew Rate (V/µs)
SR
Gain Bandwidth (MHz)
15
2.4
Gain Bandwidth (MHz)
40
GAIN BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
2.6
GBW
2.0
17
1.8
15
SR
11
1.6
1.6
10
1.4
−75
−50
−25
0
25
50
75
100
13
10
125
INPUT BIAS CURRENT
vs TEMPERATURE
30
40
50
INPUT BIAS CURRENT
vs COMMON−MODE VOLTAGE
100nA
40
10nA
35
30
Bias Current (pA)
1nA
100pA
10pA
1pA
25
20
15
−I B
+IB
10
0.1pA
5
0.01pA
−75
20
Supply Voltage (±VS)
Ambient Temperature (_C)
Input Bias Current
30
Supply Voltage (±VS)
Frequency (Hz)
0
−50
−25
0
25
50
Temperature (_ C)
4
4.0
IQ
75
100
125
−50 −40 −30 −20 −10
0
10
20
Common−Mode Voltage (V)
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30
40
50
Slew Rate (V/µs)
Voltage Gain (dB)
100
Supply Current (mA)
120
Voltage Gain (dB)
120
4.5
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VS = ±40V, unless otherwise noted.
POWER SUPPLY REJECTION
vs FREQUENCY
COMMON−MODE REJECTION
vs FREQUENCY
100
Common−Mode Rejection (dB)
Power Supply Rejection (dB)
120
100
+PSRR
80
60
−PSRR
40
20
0
90
80
70
60
50
40
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
1M
100k
10M
Frequency (Hz)
Frequency (Hz)
OPEN−LOOP GAIN
vs TEMPERATURE
POWER SUPPLY REJECTION AND
COMMON−MODE REJECTION vs TEMPERATURE
120
130
PSRR, CMRR (dB)
Voltage Gain (dB)
120
110
100
PSRR
110
100
CMRR
90
80
90
−75
−50
−25
0
25
50
75
100
70
−75
125
−25
0
25
50
75
100
Ambient Temperature (_ C)
INPUT VOLTAGE
NOISE SPECTRAL DENSITY
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
125
0.1
100
0.01
THD+Noise (%)
Voltage Noise (nV/√Hz)
−50
Ambient Temperature (_ C)
10
VO = 3.5Vrms
G = 10
0.001
VO = 3.5Vrms
VO = 10Vrms
G=1
0.0001
VO = 10Vrms
1
0.00001
10
100
1k
Frequency (Hz)
10k
100k
20
100
1k
10k 20k
Frequency (Hz)
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5
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VS = ±40V, unless otherwise noted.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
OUTPUT VOLTAGE SWING vs TEMPERATURE
(V+)
(V+)
(V+) − 1
(V+) − 4
Output Voltage Swing (V)
Output Voltage Swing (V)
(V+) − 2
(V+) − 6
Sourcing
Current
(V+) − 8
(V+) − 10
(V−) + 10
(V−) + 8
(V−) + 6
Sinking
Current
(V−) + 4
Positive Swing
(V+) − 2
(V+) − 3
(V+) − 4
(V−) + 4
(V−) + 3
Negative Swing
(V−) + 2
(V−) + 1
(V−) + 2
(V−)
(V−)
0
±5
±10
±15
±20
±25
±30
−75
−50
−25
0
Output Current (mA)
25
50
75
100
125
Temperature (_C)
SUPPLY CURRENT vs TEMPERATURE
OUTPUT CURRENT vs TEMPERATURE
35
5
30
Output Current (mA)
Supply Current (mA)
Short−Circuit Current
4
3
25
20
15
Output Current
10
VO = ±35V
5
0
2
−75
−50
−25
0
25
75
50
100
−50
125
−25
0
25
Ambient Temperature (_C)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
20
25
Percent of Amplifiers (%)
Percent of Amplifiers (%)
16
100
125
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
Typical production
distribution of
packaged units.
18
75
50
Temperature (_ C)
14
12
10
8
6
4
2
Typical production
distribution of
packaged units.
20
15
10
5
Offset Voltage (mV)
6
Offset Voltage Drift (µV/_ C)
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40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
8
10
6
4
2
0
0
5 .0
4 .5
4 .0
3 .5
3 .0
2 .5
2 .0
1 .5
1 .0
0
0 .5
− 5 .0
− 4 .5
− 4 .0
− 3 .5
− 3 .0
− 2 .5
− 2 .0
− 1 .5
− 1 .0
− 0 .5
0
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C and VS = ±40V, unless otherwise noted.
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
0.8
2.0
SO−8 PowerPAD:
TJ(max) = +125_C
No Heat Sink
0.7
Plastic DIP
1.5
TO−99
0.5
Dissipation (W)
Dissipation (W)
0.6
0.4
SO−8
Surface−Mount
(non PowerPAD)
0.3
0.2
0
T J (125 _ C max) = TA + [(|V S | − |V O |) IO × θ JA ]
θ JA = 52 _ C/W, SO−8 PowerPAD
0.5
TJ (max)
TO−99: 150_ C
DIP, SO: 125_C
0.1
1.0
(1in × 0.5in heat−spreader, 1oz Copper)
T J = 25 _ C + (1.93W × 52 _ C/W) = +125 _ C
0
−50
−25
0
25
75
50
100
−50
125
−25
0
Temperature (_C)
MAXIMUM OUTPUT VOLTAGE SWING
vs FREQUENCY
125
50
Overshoot (%)
60
50
40
30
40
G = −1
30
G = +1
20
G = −2
20
10
G = 10
10
0
1k
10k
100k
1M
0
10pF
100pF
1nF
Frequency (Hz)
Load Capacitance
SMALL−SIGNAL STEP RESPONSE
G = 1, CL = 100pF
LARGE−SIGNAL STEP RESPONSE
G = 1, CL = 100pF
10nF
10V/div
50mV/div
Output Voltage (VPP)
100
60
Maximum output
without slew−rate
induced distortion.
70
75
50
SMALL−SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
90
80
25
Temperature (_C)
500ns/div
2.5µs/div
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7
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
INPUT PROTECTION
APPLICATIONS
Figure 1 shows the OPA445 connected as a basic
noninverting amplifier. The OPA445 can be used in
virtually any op amp configuration.
Power-supply terminals should be bypassed with 0.1µF
capacitors, or greater, near the power supply pins. Be sure
that the capacitors are appropriately rated for the
power-supply voltage used.
V+
The inputs of conventional FET-input op amps should be
protected against destructive currents that can flow when
input FET gate-to-substrate isolation diodes are
forward-biased. This can occur if the input voltage
exceeds the power supplies or there is an input voltage
with VS = 0V. Protection is easily accomplished with a
resistor in series with the input. Care should be taken
because the resistance in series with the input
capacitance may affect stability. Many input signals are
inherently current-limited; therefore, a limiting resistor may
not be required.
0.1µF
G = 1+
R1
R2
R1
OFFSET VOLTAGE TRIM
R2
VO
OPA445
VIN
ZL
0.1µF
The OPA445 provides offset voltage trim connections on
pins 1 and 5. Offset voltage can be adjusted by connecting
a potentiometer as shown in Figure 2. This adjustment
should be used only to null the offset of the op amp, not to
adjust system offset or offset produced by the signal
source. Nulling system offset could degrade the offset
voltage drift behavior of the op amp. While it is not possible
to predict the exact change in drift, the effect is usually
small.
V−
Figure 1. The OPA445 Configured as a
Noninverting Amplifier
Use offset adjust pins
only to null offset voltage
of op amp−see text.
V+
POWER SUPPLIES
The OPA445 may be operated from power supplies up to
±45V or a total of 90V with excellent performance. Most
behavior remains unchanged throughout the full operating
voltage range. Parameters which vary significantly with
operating voltage are shown in the Typical Characteristics.
Some applications do not require equal positive and
negative output voltage swing. Power-supply voltages do
not need to be equal. The OPA445 can operate with as little
as 20V between the supplies and with up to 90V between
the supplies. For example, the positive supply could be set
to 80V with the negative supply at −10V, or vice-versa.
8
7
2
6
OPA445
1
3
5
10mV Typical
Trim Range
4
(1)
V−
NOTE: (1) 10kΩ to 1MΩ
Trim Potentiometer
(100kΩ recommended).
Figure 2. Offset Voltage Trim
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""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
CAPACITIVE LOADS
INCREASING OUTPUT CURRENT
The dynamic characteristics of the OPA445 have been
optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop
gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Figure 3
shows a circuit which preserves phase margin with
capacitive load. The circuit does not suffer a voltage drop
due to load current; however, input impedance is reduced
at high frequencies. Consult Application Bulletin
SBOA015, available for download at www.ti.com, for
details of analysis techniques and application circuits.
In those applications where the 15mA of output current is
not sufficient to drive the required load, output current can
be increased by connecting two or more OPA445s in
parallel as shown in Figure 4. Amplifier A1 is the master
amplifier and may be configured in virtually any op amp
circuit. Amplifier A2, the slave, is configured as a unity gain
buffer. Alternatively, external output transistors can be
used to boost output current. The circuit in Figure 5 is
capable of supplying output currents up to 1A.
R1
R1
R2
2kΩ
2kΩ
RC
20Ω
R2
Master
OPA445
G=1+
VIN
R2
R1
CC
0.22µF
OPA445
RS(1)
10Ω
RS(1)
10Ω
VO
VIN
OPA445
RC =
CC =
CL
5000pF
R2
Slave
2CL × 1010 − (1 + R2 /R1)
CL × 103
RC
NOTE: (1) RS resistors minimize the circulating
current that will always flow between the two devices
due to VOS errors.
NOTE: Design equations and component values are approximate.
User adjustment is required for optimum performance.
Figure 3. Driving Large Capacitive Loads
R1
RL
Figure 4. Parallel Amplifiers Increase Output
Current Capability
R2
+45V
TIP29C
CF
(1)
R3
100Ω
R4
0.2Ω
VO
OPA445
VIN
R4
0.2Ω
LOAD
TIP30C
−45V
NOTE: (1) Provides current limit for OPA445 and allows the amplifier to
drive the load when the output is between +0.7V and −0.7V.
Figure 5. External Output Transistors Boost Output Current Up to 1 Amp
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""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
SAFE OPERATING AREA
100
The safe output current decreases as VS − VO increases.
Output short-circuits are a very demanding case for SOA.
A short-circuit to ground forces the full power supply
voltage (V+ or V−) across the conducting transistor and
produces a typical output current of 25mA. With ±40V
power supplies, this creates an internal dissipation of 1W.
This exceeds the maximum rating and is not
recommended. If operation in this region is unavoidable,
a heat sink is required. For further insight on SOA, consult
Application Bulletin SBOA022 (available for download at
www.ti.com).
Output Current (mA)
TA = 25_C
10
TA = 125_ C
TA = 85_ C
TA + [(|VS| − |VO|) I O × θ JA] ≤ TJ (max)
θ JA = 200_C/W (No Heat−Sink)
TJ (max) = 150_C
NOTE: Simple clip−on heat−sinks can
reduce θ by as much as 50_ C/W.
1
0.1
1
2
20
10
50
100
Figure 7. TO-99 Safe Operating Area
100
TA = 25_C
10
TA = 85_ C
TA = 120_C
1
TA + [(|VS | − |VO|) IO × θ JA ] ≤ TJ (max)
θ JA = 150_C/W
TJ (max) = 125_C
0.1
100
1
2
TA = 25_ C
5
20
10
50
100
|VS| − |VO| (V)
Figure 8. SO-8 (non PowerPAD) Safe Operating
Area
10
TA = 85_C
TA = 120_ C
100
TA = 25_ C
1
TA + [(|VS | − |VO|) IO × θ JA ] ≤ TJ (max)
θ JA = 100_C/W
TJ (max) = 125_C
0.1
1
2
5
10
20
50
|VS| − |VO| (V)
100
Output Current (mA)
Output Current (mA)
5
|VS| − |VO| (V)
Output Current (mA)
Stress on the output transistors is determined both by the
output current and by the output voltage across the
conducting output transistors, VS − VO. The power
dissipated by the output transistor is equal to the product
of the output current and the voltage across the conducting
transistor, VS − VO. The Safe Operating Area (SOA curve,
Figure 6 through Figure 10) illustrates the permissible
range of voltage and current. The curves shown represent
devices soldered to a printed circuit board (PCB) with no
heat sink. Increasing printed circuit trace area or the use
of a heat sink (TO-99 package) can significantly reduce
thermal resistance (q ), resulting in increased output
current for a given output voltage (see Figure 11,
Figure 12, and the Heat Sink section).
10
TA = 85_C
TA = 120_C
1
TA + [(|VS| − |VO|) IO × θ JA] ≤ TJ (max)
θ JA = 96_ C/W
TJ (max) = 125_C
Figure 6. DIP-8 Safe Operating Area
0.1
1
10
100
|VS| − |VO| (V)
Figure 9. SO-8 PowerPAD Safe Operating Area
(no heat-spreader, no airflow)
10
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
POWER DISSIPATION
100
Output Current (mA)
1in x 0.5in, 1oz Cu
Power dissipation depends on power supply, signal, and
load conditions. For dc signals, power dissipation is equal
to the product of the output current times the voltage
across the conducting output transistor, PD = IL (VS − VO).
Power dissipation can be minimized by using the lowest
possible power-supply voltage necessary to assure the
required output voltage swing.
TA = 25_ C
TA = 85_ C
10
TA = 120_C
1
TA + [(|VS| − |VO|) IO × θ JA] ≤ TJ (max)
θ JA = 52_C/W
TJ (max) = 125_ C
0.1
1
100
10
|VS| − |VO| (V)
Figure 10. SO-8 PowerPAD Safe Operating Area
(with heat-spreader, no airflow)
Thermal Resistance, θ JA (_ C/W)
120
100
No Heat−Spreader
For resistive loads, the maximum power dissipation occurs
at a dc output voltage of one-half the power supply voltage.
Dissipation with ac signals is lower. Application Bulletin
SBOA022 explains how to calculate or measure
dissipation with unusual loads or signals.
The OPA445 can supply output currents of 15mA and
larger. This would present no problem for a standard op
amp operating from ±15V supplies. With high supply
voltages, however, internal power dissipation of the op
amp can be quite large. Operation from a single power
supply (or unbalanced power supplies) can produce even
larger power dissipation since a large voltage is impressed
across the conducting output transistor. Applications with
large power dissipation may require a heat-sink.
80
HEAT SINKING
60
With Heat−Spreader, 1in x 0.5in, 1oz Cu
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Air−Flow (meters/sec)
Figure 11. SO-8 PowerPAD Thermal Resistance
(with and without heat-spreader)
Thermal Resistance, θ JA (_ C/W)
100
No Airflow
90
80
70
60
50
Power dissipated in the OPA445 will cause the junction
temperature to rise. For reliable operation junction
temperature should be limited to 125°C, maximum (150°C
for TO-99 package). Some applications will require a
heat-sink to assure that the maximum operating junction
temperature is not exceeded. In addition, the junction
temperature should be kept as low as possible for
increased reliability. Junction temperature can be
determined according to the following equation:
T J + T A ) PD q JA
(1)
Package thermal resistance, qJA, is affected by mounting
techniques and environments. Poor air circulation and use
of sockets can significantly increase thermal resistance.
Best thermal performance is achieved by soldering the op
amp into a circuit board with wide printed circuit traces to
allow greater conduction through the op amp leads.
Simple clip-on heat sinks (such as a Thermalloy 2257) can
reduce the thermal resistance of the TO-99 metal package
by as much as 50°C/W. The SO-8 PowerPAD package will
provide lower thermal resistance, especially with a simple
heat-spreader—even lower with a heat-sink. For
additional information on determining heat-sink requirements, consult Application Bulletin SBOA021.
40
30
0
0.5
1.0
1.5
2.0
2.5
3.0
Copper Area (inches2)
Figure 12. Thermal Resistance vs Circuit Board
Copper Area
www.BDTIC.com/TI
11
""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
PowerPAD THERMALLY-ENHANCED
PACKAGE
In addition to the SO-8, DIP-8, and TO-99 packages, the
OPA445 also comes in an SO-8 PowerPAD. The SO-8
PowerPAD is a standard-size SO-8 package where the
exposed leadframe on the bottom of the package can be
soldered directly to the PCB to create an extremely low
thermal resistance. This architecture enhances the
OPA445’s power dissipation capability significantly and
eliminates the use of bulky heatsinks and slugs
traditionally used in thermal packages. This package can
be easily mounted using standard PCB assembly
techniques. NOTE: Since the SO-8 PowerPAD is
pin-compatible with standard SO-8 packages, the
OPA445 can directly replace operational amplifiers in
existing sockets. Soldering the PowerPAD to the PCB is
always required, even with applications that have low
power dissipation. Soldering the device to the PCB
provides the necessary thermal and mechanical
connection between the leadframe die pad and the PCB.
The PowerPAD package is designed so that the leadframe
die pad (or thermal pad) is exposed on the bottom of the
IC; see Figure 13. This design provides an extremely low
thermal resistance (qJC) path between the die and the
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the
PCB as a heatsink. In addition, plated-through holes (vias)
provide a low thermal resistance heat flow path to the back
side of the PCB.
Leadframe (Copper Alloy)
IC (Silicon)
Mold Compound (Plastic)
Die Attach (Epoxy)
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat-dissipating device. Soldering
the PowerPAD to the PCB is always required, even with
applications that have low power dissipation. Follow these
steps:
1.
The PowerPAD must be connected to the most
negative supply voltage on the device, V−.
2.
Prepare the PCB with a top-side etch pattern. There
should be etching for the leads as well as etch for the
thermal pad.
3.
Place recommended holes in the area of the thermal
pad. Recommended thermal land size and thermal via
patterns for the SO-8 DDA package is shown in
Figure 14. These holes should be 13 mils in diameter.
Keep them small, so that solder wicking through the
holes is not a problem during reflow. The minimum
recommended number of holes for the SO-8
PowerPAD package is five.
4.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. These
vias help dissipate the heat generated by the OPA445
IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can
be larger because they are not in the thermal pad area
to be soldered; thus, wicking is not a problem.
5.
Connect all holes to the internal power plane of the
correct voltage potential (V−).
6.
When connecting these holes to the plane, do not use
the typical web or spoke via connection methodology.
Web connections have a high thermal resistance
connection that is useful for slowing the heat transfer
during soldering operations, makeing the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. Therefore,
the holes under the OPA445 PowerPAD package
should make the connections to the internal plane with
a complete connection around the entire
circumference of the plated-through hole.
7.
The top-side solder mask should leave the terminals
of the package and the thermal pad area exposed.
The bottom-side solder mask should cover the holes
of the thermal pad area. This masking prevents solder
from being pulled away from the thermal pad area
during the reflow process.
8.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
Leadframe Die Pad
Exposed at Base of the Package
(Copper Alloy)
Figure 13. Section View of a PowerPAD Package
GENERAL PowerPAD LAYOUT GUIDELINES
The OPA445 is available in a thermally-enhanced
PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package. This thermal
pad has direct thermal contact with the die; thus, excellent
thermal performance is achieved by providing a good
thermal path away from the thermal pad.
12
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""#
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SBOS156B − MARCH 1987 − REVISED APRIL 2008
9.
With these preparatory steps in place, the PowerPAD
IC is simply placed in position and run through the
solder reflow operation as any standard surfacemount
component. This preparation results in a properly
installed part.
Thermal Land
(Copper)
Minimum Size
4.8mm x 3.8mm
(189 mils x 150 mils)
O PTIONAL:
Additional four vias outside
of thermal pad area but
under the package.
For detailed information on the PowerPAD package,
including thermal modeling considerations and repair
procedures, see technical brief SLMA002 PowerPAD
Thermally-Enhanced Package available for download at
www.ti.com.
REQUIRED:
Thermal pad area 2.286mm x 2.286mm
(90 mils x 90 mils) with five vias
(via diameter = 13 mils)
Figure 14. 8-Pin PowerPAD PCB Etch and Via
Pattern
TYPICAL APPLICATIONS
R1
100kΩ
R2
10kΩ
V1
+60V
0.1µF
+40V
25kΩ
OPA445
−40V
V2
OPA445
VO = 0V to +50V
at 10mA
Protects DAC
During Slewing
R4
9.9kΩ
R3
100kΩ
0−2mA
DAC8811
or
DAC7811
R5
100Ω
0.1µF
Load
IL
IL = [(V2 − V1)/R5] (R2 /R1)
= (V2 − V1)/1kΩ
−12V
Compliance Voltage Range = ±35V
NOTE: R 1 = R3 and R2 = R4 + R5
Figure 15. Voltage-to-Current Converter
R1
1kΩ
Figure 16. Programmable Voltage Source
R2
9kΩ
R3
10kΩ
R4
10kΩ
+45V
+45V
160V
OPA445
VIN
±4V
OPA445
Slave
Piezo(1)
Crystal
Master
−45V
−45V
NOTE: (1) For transducers with large capacitance the stabilization
technique described in Figure 6 may be necessary. Be certain that the
Master amplifier is stable before stabilizing the Slave amplifier.
Figure 17. Bridge Circuit Doubles Voltage for Piezo Crystals
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13
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA445ADDA
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA445ADDAG4
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA445ADDAR
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA445ADDARG4
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA445AP
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA445APG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
OPA445AU
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA445AU/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA445AU/2K5E4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA445AUG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA445BM
NRND
TO-99
LMC
8
20
Green (RoHS &
no Sb/Br)
AU
Lead/Ball Finish
MSL Peak Temp (3)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2009
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
www.BDTIC.com/TI
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA445ADDAR
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA445AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
www.BDTIC.com/TI
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA445ADDAR
SO PowerPAD
DDA
8
2500
346.0
346.0
29.0
OPA445AU/2K5
SOIC
D
8
2500
346.0
346.0
29.0
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Pack Materials-Page 2
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