How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using

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How to anticipate Signal Nilesh Kamdar
Integrity Issues: Application Engineer
Improve my Channel Agilent EEsof EDA
Simulation by using
Electromagnetic based
model
HSD Strategic Intent
Provide the industry’s premier HSD EDA software.
– Integration of premier simulation technologies for microwave effects (which are
inherent in the multigigabit/s regime), tuned to the needs of high speed digital designers.
Key Technology Investments
IC Model Builder:
SystemVue
HSD Designer:
ADS/EMPro
Physical Designer:
Constraint-based tool e.g.
Allegro, Expedition,
CR-5000 etc.
Outline
• Pre-Layout “Getting to know the Channel”
EM for Component Modeling
•
Extraction of High Frequency PCB Material Properties
•
Accurate Time skew
•
Connector footprint and Via modeling
• Post-Layout “Avoiding costly Re-Spins”
Full-Path EM Simulations
•
Thales Testcase
High Density 4000 HD Connections
•
Agilent Example
HSD board along with SATA and USB connectors
• Conclusion
Outline
• Pre-Layout “Getting to know the Channel”
EM for Component Modeling
•
Extraction of High Frequency PCB Material Properties
•
Accurate Time skew
•
Connector footprint and Via modeling
• Post-Layout “Avoiding costly Re-Spins”
Full-Path EM Simulations
•
Thales Testcase
High Density 4000 HD Connections
•
Agilent Example
HSD board along with SATA and USB connectors
• Conclusion
HSD Design Flow – “Getting to Know the Channel”
CHECKLIST
PRE-LAYOUT
Component
3D-EM
Model
Building
Design
Constraints

Design Topology Exploration

Component Selection

Tx and Rx Model Validation

Optimized Design Constraints
Channel
Simulator
Optimize
t and f
Engineer the topology and simulate the design constraints!
Pre-Layout Co-Simulation with EM Simulators
Channel co-simulation
with PCB EM model
including crosstalk and
8B10B encoding
EM Model
3D-EMPro
Connector
Model
With 8B10B Coding
Generation of Design Constraints
Agilent EM Simulation Portfolio
ADS
EMPro
Parameterized
3D EM Components
ADS Layout Export
EMDS-for-ADS
Momentum Simulator
FEM Simulator
FDTD Simulator
Method of Moments
Finite Element Method
Finite Difference Time Domain
Planar Simplifications
3D Accuracy
Time Domain Excitation
Constraint Examples for Impedance Mismatch
Stub Resonance
5 GB/s, PRBS 7
1mm
Stub
10 mm
Stub
5 GB/s, PRBS 7
Series Resonance
1 mm
25 mm
Signal Loss S21
1mm
Mismatch
25 mm
Mismatch
HSD Design Flow – “Getting to Know the Channel”
Benefits in using 3DEM in Pre-Layout
PRE-LAYOUT
Component
3D-EM
Model
Building
Design
Constraints
Channel
Simulator

Extraction of High Frequency PCB Material
Properties

Accurate Time skew

Connector footprint and Via modeling
Optimize
t and f
Capturing the physics of components in the channel
Measurement Based Verification of EM Simulation
Simple Series Resonant Change in Impedance
EM Simulations are
only as accurate as the
PCB specifications
EM Simulation Fails to Match Measurement
Frequency Domain
Time Domain
PCB Conductor and Dielectric Material Properties
PCB Frequency Dependent Losses
can be separated into Conductor
and Dielectric Losses
Stripline Conductor Losses require
more then 1 line width to determine
dielectric height and trace width.
Stripline Dielectric Losses only
require 1 line length to determine
dielectric loss and electrical delay.
α dB = α cond + α diel
α cond
α diel =
36
=
wZ 0
π
co
f
 2b + t 
Ζο =
ln

ε r  0.8w + t 
60
f tan δ ε r
Z0, characteristic impedance (Ohm)
b, the dielectric height between reference planes (mil)
t, copper thickness of the PCB trace (mil)
w, trace width (mil)
ε r , dielectric constant
co , is the speed of light in vacuum
tan δ , loss tangent
Typical Method for Measured PCB Material Properties
Two PCB Test Structures with Different Line Lengths
 Excellent for determining T-Line loss and delay characteristics
 Does not provide information on as-built trace width and dK height.
FIXTURE A
S-PARAMETERS
SYMMETRICAL 2x FIXTURE
THROUGH PATH
FIXTURE B
S-PARAMETERS
Step 1
Splitting of the
S-Parameters
Agilent PLTS
AFR Algorithm
FIXTURE + ADDITIONAL LINE LENGTH
Step 2
FIXTURE
DE-EMBED
T-Matrix
T-LINE LENGTH
MATERIAL PROPERTIES
Additional PCB Resonant Beatty Structure
Beatty Style Series Resonant Change in Impedance Test Structure
 Enables estimation of as-fabricated dK height and trace width.
 Only requires one additional test structure on the PCB.
 Simple layout construction.
FIXTURE + Resonant Beatty Structure
Step 3
T-Line Change in Z
Fabrication Properties
FIXTURE
DE-EMBED
T-Matrix
S-Parameters before Fixture De-Embed
Step 3
FIXTURE
DE-EMBED
Measured S-Parameters
after Fixture De-Embed
Enables Estimate of Trace Width and DK Height
Series Resonant Beatty Structure
As-Fabricated
Material Properties
Dielectric Constant
Loss Tangent
Dielectric Height
Trace Width
Etching Tolerance
Trace thickness
Copper Trace Conductivity
Tune Model Variables
to Match Measurement
Var
Eqn
VAR
VAR6
Er=3.22 {t}
b=7.9 {t}
W=9.4 {t}
W_tol=-1.1 {t}
TanD=0.0058328 {t}
t=0.6
sigma=42936000 {t}
2-Step Process: Fast Tuning with 2D-Planar Model
then Fine Tune with EM Simulator
Fast Tune 2D-Planar Model Parameters to Match Measured Data
* Simple T-Line model with out the complexity of fixture connections
Matching Measured Data – Time and Frequency
Transmission Line Through Segment
Series Resonant Beatty Structure
Final 3D EM Model vs. Measurement
Fine Tune EM Model Parameters to Match Measured Data
Frequency Domain
3D EM Model
Time Domain
•
•
•
•
•
•
Parameters for Tuning
Dielectric Constant
Dielectric Height
Trace Width
Etching Tolerance
Loss Tangent
Copper Trace Conductivity
HSD Design Flow – “Getting to Know the Channel”
Benefits in using 3DEM in Pre-Layout
PRE-LAYOUT
Component
3D-EM
Model
Building
Design
Constraints
Channel
Simulator

Extraction of High Frequency PCB Material
Properties

Accurate Time skew

Connector footprint and Via modeling
Optimize
t and f
Capturing the physics of components in the channel
DDR4 PCB Layout Design Rules
Losses, Crosstalk, and EMI

Routing Impedance
 Via Transitions

Trace Width and Spacing
 Reference Plane Transitions

Material stack-up
 PDN Impedance

BGA Trace Necking
 Skew Routing Compensation
DDR DQ Byte Lane Model for Design Exploration
Model Variables
Available for Tuning,
Optimizing, and Design
of Experiments
DDR Skew Compensation with Serpentine Routing
Source Synchronous Clocking of DQ Byte Lanes Requires Matched Channel Lengths
Squeezing a Transmission Line While Maintaining
its Length
ADS Layout allows to modify an existing transmission line to
squeeze it into a smaller space, specifying several
characteristics in the process, such as corner type, lead length
and minimum spacing.
Electrical Length not Physical Length for DDR4
Minimum Bends “Switchback” Routing
Maximum Bends “Serpentine” Routing
PHYSICAL LENGTH MATCHING
Start: Edges Aligned
33 mm Matched Length
ELECTRICAL LENGTH MATCHING
Edges Aligned, No Skew
31 mm
33 mm
End: Edges are Skewed 12pS
2 mm Length Difference
Electrical Length not Physical Length for DDR4
Limited PCB Routing Space – Maximizing Density
Serpentine with minimum layout width
requires significantly more length for
skew matching as compared to
switchback routing.
Switchback routing results in less skew when utilizing
Physical Lengths in a PCB CAD tool for length matching.
HSD Design Flow – “Getting to Know the Channel”
Benefits in using 3DEM in Pre-Layout
PRE-LAYOUT
Component
3D-EM
Model
Building
Design
Constraints
Channel
Simulator

Extraction of High Frequency PCB Material
Properties

Accurate Time skew

Connector footprint and Via modeling
Optimize
t and f
Capturing the physics of components in the channel
Connector footprint and Via modeling
One commonly overlooked source of channel discontinuity is the
signal via. Vias can add jitter and reduce eye openings that can cause
data misinterpretation by the receiver.
3DEM simulation can be used to evaluate / optimize:
•
•
•
•
•
•
•
Impedance signatures
Insertion / Return losses
GND Return Vias
Pads and Anti-Pads
Via stubs
Backdrilling
PCB Stackup
SMA Footprint
PCB Layout
Evaluate S-parameter profiles for a
standard SMA footprint using PTH for 2
different cases:
-
ETCH_TOP to ETCH_INT3 (long
stub)
PCB Stackup
ETCH_TOP to ETCH_INT10 (short
stub)
Where:
-
ETCH_INT4 and ETCH_INT9 are
power planes
-
ETCH_INT5 and ETCH_INT8 are
GND planes
SIG
PWR
GND
GND
PWR
SIG
Momentum simulation
step by step
1. Mesh - Discretizing the problem
Core simulation technology
improvements
2. Load – Filling the matrix - NlogN
column j
row i
Zij
3. Solve – Solving the matrix - NlogN
S-Parameter simulation results
Longer via stub lengths cause larger
impedance discontinuity and present
more loss to the signal path.
You can eliminate the via stub by
routing only microstrip traces on the
top and bottom layers of the board.
However, this might not be possible
because of layout constraints,
electromagnetic interference (EMI)
related concerns, or other board
design considerations with microstrip
traces.
Long stub
Short stub
Current visualization versus frequency
150 MHz
8,8 GHz
14 GHz
ETCH_TOP
to
ETCH_INT3
150 MHz
ETCH_TOP
to
ETCH_INT10
8,8 GHz
14 GHz
Current
visualization can
help in identifying
root causes of
unexpected
resonances
Outline
• Pre-Layout “Getting to know the Channel”
EM for Component Modeling
•
Extraction of High Frequency PCB Material Properties
•
Accurate Time skew
•
Connector footprint and Via modeling
• Post-Layout “Avoiding costly Re-Spins”
Full-Path EM Simulations
•
Thales Testcase
High Density 4000 HD Connections
•
Agilent Example
HSD board along with SATA and USB connectors
• Conclusion
HSD Design Flow – “Avoiding costly Re-Spins”
CHECKLIST
POST-LAYOUT
Full-Path
3D-EM
Layout
Import
Channel
Design
Verify

Verify the layout before Fabrication

Full 3D EM extraction for Accurate models

Meet all the Requirements
Simulator
Power
Integrity
Avoiding costly Re-Spins with full-path Electro-Magnetic simulation
Design Challenge - Radiation and Coupling Loss
EM simulation for complex
radiation and crosstalk.
Identical
12mil Traces, 5mil Gap
Microstrip 5Gbps Eye
Microstrip Loss
Microstrip FEXT
MICROSTRIP
Stripline 5Gbps Eye
Stripline Loss
STRIPLINE
Stripline FEXT
Post-Layout ADFI for Importing PCB Designs
1 Layer Selection Tools
and Fabrication Details
2
Intelligent Net Selection
Cookie Cutting
5
4 EM S-Parameter Model DQ Signal Eye Diagrams
Co-Simulation
EM
Model
EM
Model
3
EM Simulation
6 DDR Compliance Report
HSD Design Flow – “Avoiding costly Re-Spins”
Benefits in using 3DEM in Post-Layout
POST-LAYOUT
Full-Path
3D-EM
Layout
Import
Channel
Design
Verify

Thales Testcase
High Density 4000 HD Connections

Agilent Example
HSD board along with SATA and USB
connectors
Simulator
Power
Integrity
Avoiding costly Re-Spins with full-path Electro-Magnetic simulation
Copyright 2012 Agilent Technologies, Inc.
36
Copyright 2012 Agilent Technologies, Inc.
37
Copyright 2012 Agilent Technologies, Inc.
38
Copyright 2012 Agilent Technologies, Inc.
39
Agressor
Signal Path
Agressor
Copyright 2012 Agilent Technologies, Inc.
40
Copyright 2012 Agilent Technologies, Inc.
41
HSD Design Flow – “Avoiding costly Re-Spins”
Benefits in using 3DEM in Post-Layout
POST-LAYOUT
Full-Path
3D-EM
Layout
Import
Channel
Design
Verify

Thales Testcase
High Density 4000 HD Connections

Agilent Example
HSD board along with SATA and USB
connectors
Simulator
Power
Integrity
Avoiding costly Re-Spins with full-path Electro-Magnetic simulation
HSD board along with SATA and USB connectors
Testcase overview
In such applications, the main
cause of impedance
discontinuities and crosstalk is
the area where the connector is
attached to the RF board
differential traces, so without
taking complete integrated
system into SI consideration, it is
difficult to get accurate answers
and error-prone solution.
HSD board along with SATA and USB connectors
EM simulation using Finite Element Method solver
Hot spots
Return Loss
Insertion Loss
HSD board along with SATA and USB connectors
Post Layout Analysis of complete system
Channel Simulation with a single TX_Diff
component and no crosstalk effect in ADS
Enable the DFE in the "Rx_Diff"
to get the better Eye Opening
Eye_Probe
Eye_Probe1
Vin
Rx
Rx_Diff
Rx_Diff1
ExcludeLoad=no
EnableCTLE=no
EnableFFE=no
EnableDFE=no
Differential Trace:
The Bit Rate is taken as = 1 Gbps
ChannelSim
ChannelSim
ChannelSim1
NumberOfBits=1000
ToleranceMode=Auto
EnforcePassivity=yes
Tx
Tx_Diff
Tx_Diff1
BitRate=1 Gbps
Vhigh=1.0 V
Vlow=0.0 V
RiseFallTime=100 psec
Mode=Maximal Length LFSR
ExcludeLoad=yes
EQMode=Specify FIR taps
Term_Diff
Term_Diff5
Load=100 Ohm
Term_Diff
Term_Diff6
Load=100 Ohm
Term_Diff
Term_Diff7
Load=100 Ohm
EM_SATA_USB_Converter_System
emModel
X1
Term_Diff
Term_Diff2
Load=100 Ohm
Outline
• Pre-Layout “Getting to know the Channel”
EM for Component Modeling
•
Extraction of High Frequency PCB Material Properties
•
Accurate Time skew
•
Connector footprint and Via modeling
• Post-Layout “Avoiding costly Re-Spins”
Full-Path EM Simulations
•
Thales Testcase
High Density 4000 HD Connections
•
Agilent Example
HSD board along with SATA and USB connectors
• Conclusion
Conclusion
High Density 4000 HD Connections
Low Cost MEMORY DIMM
C. Chastang, et al.. “An Innovative Simulation Workflow for
Debugging High-Speed Digital Designs using Jitter
Separation, , SPI 2013”
 High density complex designs with analog, digital, and an array of power
supplies leads to complex electromagnetic interactions that are best
evaluated by full EM simulation.
 High volume low cost resulting in highly perforated power and ground
planes with non-ideal return currents rely on EM simulators to predict the
true interactions in the multi-gigabit domain.
Backup slides
Comment on Measured Data Accuracy
Measured vs 3D-EM Simulated
Measurement Accuracy
Quality of the Fixture
3D EM - FEM
Requires Symmetry
~3D EM - MOM
Measurement
Measure
Model

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