BVA™ Technology Enabling the Next Generation of Ultra

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BVA™ Technology
Enabling the Next Generation of
Ultra-fine Pitch Wide IO
Package-on-Package
Rajesh Katkar, Rey Co and Wael Zohni
Invensas Corp.
•Package-on-Package (PoP) for Mobile
• Requirements/Trends
•Invensas Bond-Via-Array (BVA)
• Description, PoP application
•BVA Package Development
• Engineering, HVM readiness
•Summary
•Q&A
Apple iPhone 5S Smartphone
Amazon Kindle Fire HDX Tablet
Samsung Galaxy Tab 3 Tablet
Sony Cyber-Shot DSC-QX10 Camera
Source: UBM TechInsights (www.teardown.com)
•
•
Reduced form factor
“All-in-one” Functionality:
• Product
• Component (SoC)
Source: Evernote
• Improved graphics
• (HD, 4K, 3D gaming)
• Multi-screen operation
• Extended battery life
* Source: Samsung, Apple, and EA Sports images



Increased memory bandwidth with lowered power
New wide I/O DRAM standard specifies 4 128-bit channels
Current PoPs do not support required this level of I/O count
1000 I/O
SC
512 I/O
256 I/O
Source: Intel
Higher Input/Output (I/O) Enables Lower Frequency Operation = Less Power

BVA = Bond Via Array
◦ High-density, fine-pitch vertical interconnect that leverages
existing wirebond capabilities
◦ Enables next-generation compact 3D component integration without
need for new equipment
◦ Bridges stacking technology gap between current packaging and
future 3D concepts such as TSV
BVA Cross-section:
high aspect ratio vertical wirebonds
0.240mm pitch
(future
)
Minimum
Pitch (µm)
450um
350
<150
40
Maximum
# of IO*
350
520
1600+
4000+
* 14x14mm pkg

BVA offers advantages of TSV while utilizing existing packaging materials
650
Through-Mold –Via (TMV)
600
128
BGA stack
550
Interconnect pitch (µm)
450
400
BVA
512
350
300
1024
250
200
150
2048
100
50
0
4096
0
50
100
150
200
250
300
Interconnect height (µm)

350
400
450
500
BVA substantially improves the pitch and number of IO while being
independent of the interconnect height (distance between logic and
memory substrates)
Number of interconnects
256
500
BVA PoP Features
Top View
Memory-Logic Interface
Side View

Bond Via Array (BVA)


Stand-off issue eliminated: Wire-bond
based memory-logic interconnect
1000+ wide IO: fine pitch capability
High performance at low-cost:
Conventional PoP materials, equipment
and process
Test Vehicle Design – 1020 IO
14 mm x 14 mm
1.25 mm
0.4 mm x 0.4
mm
916
Number of bottom IO
0.24 mm x 0.24
Top IO pitch
mm
5
Number of IO rows
1020
Number of top IO
Package size
Package thickness
Bottom IO pitch

1020 memory-logic
interconnects at 0.24 mm x 0.24
mm pitch providing wide IO PoP
implementation.
Test Vehicle Design – Substrates
Logic Substrate Top View


Memory Substrate Bottom View
Logic substrate has flip-chip pads at the center and wire-bond pads at
periphery
Memory substrate has solder pads only along the periphery
BVA PoP Process Flow
Flux dip /
mount top
(memory)
package

Conventional industry
equipment and processes are
used for BVA assembly
BVA PoP Assembly Highlights
BVA Formation:
Wire-tip positional tolerance
Molding and tip exposure:
Clean wire tips
BVA PoP Assembly Highlights
PoP Stacking
High yield

Extensive engineering development of HVM process utilizing established
wirebond platform
BVA Formation: Process
50um Wire





Photo: Courtesy of
Kulicke & Soffa
Co-developed vertical wirebond process with K&S
Robust process using conventional K&S ICONN bonder
Verified volume production feasibility
High positional accuracy, through-put and yield
Transferable process to other platforms including Shinkawa
and ASM
Molding and Wire-Tip Exposure
Mold Tool
Mold Film
Overmold
Photo:
Courtesy of APIC
Yamada Corp.
G-Line Mold Machine
Critical process parameters
verified in cooperation with
Yamada mold
 Established production process
that ensures uniform and clean
wire tips

Film Assist Mold
May 27 – 30, 2014
21
Wire-Tip Cleaning
Before Mold De-Flash
After Mold De-Flash
Trialed both mechanical and chemical methods for removal of mold
residue
 Inspection and process results after plasma de-flash confirm effective
cleaning

Wire tip, BGA, and PKG Position Data
• Measured relative position of wire-tips, to BGA grid outline for individual units.
• Positional tolerance within specifications and alignment capability of socket
Memory and Logic Package Test Socket
Drawing: Courtesy of Leeno and SemiQual

Pre and post-socket test inspections indicates
robust wire tips
Pre-socketing
Post-socketing
• Minimal Deformation of BVA tips using Conventional Pin-Type Socket
PoP Stacking: Process
Memory Package


Top and bottom
packages joined using
conventional PoP SMT
equipment
High yielding & reworkable soldering
process
UIC Advantis3
Photo:
Courtesy of Universal Instruments
Logic Package
BVA PoP Package
1020-IO BVA PoP Reliability Tests
Test
Standard
Test Condition
Sample
Results
MSL: Level3
IPC / JEDEC
J-STD-020C
125°C for 24hrs;
30°C/60%RH for
192 hrs, 3X Pb-free
reflow
22
Pass
Temperature
Cycling (Board
Level)
JESD22A104D
Condition G
-40°C to 125°C,
1000 cycles
45
Pass
High
Temperature
Storage
JESD22A103D
Condition B
150°C, 1000 hrs
22
Pass
JESD22-B111
>30drops, 1500Gs,
0.5mSec of half
sine pulse
20
Pass
Drop Testing
•
•
•
A small sample size also passed biased-HAST test (JESD22-A110C: 130C, 85%RH,96hrs) at 51mA
bias; full test with JEDEC recommended sample size is being scheduled
BVA interconnects in High temperature storage parts were underfilled
Board level temperature cycling was performed with non-underfilled (and underfilled) BVA
interconnects
Temperature Cycling Test:
• Test units without underfill between bottom and top package included for TCT
• Components had only BGA of the logic underfilled to the test board
• JESD-A104G (-40°C to 125°C, 1000 cycles)
• All parts passed e-testing after 1500 cycles; further testing ongoing
BVA PoP at the package corner after 1000 TCT
Survived
500 drops
Drop Test:
• JESD22-B111 (>30drops, 1500Gs, 0.5mS of 1/2 sine pulse)
• Only Logic BGA was underfilled on PCB test board; BVA interconnects were not underfilled
• All parts passed JEDEC test requirement of 30 drops. 1st failure after 181 drops; MTTF:
354 drops
• Fail mode: crack initiation in corner BVA bumps and propagated vertically along the Cu wire
• The significantly better performance of the BVA interconnects attributed to:
• Pd coated Cu wires significantly reduces the IMC growth, improving its overall reliability
• Total 1020 wires supporting the memory significantly reduces stress/joint
• The optimized mold bleed removal allows uniform solder coverage and a better joint
• Wire tip formation optimized to:
• Minimize post-mold flash deposit thus reducing or eliminating cleaning steps
• Increase mechanical robustness for assembly handling and socketing
Phase-1
Tapered
Wire tips
Optimized
Sharp-Tips
• Current BVA PoP package utilizes 2mil (50um) diameter Cu wires
• Packages with 1.5mil Cu wires have been fabricated
• Testing and evaluation of 1.5mil wire units ongoing
Pre-Mold
Post-Mold
Developing Reduced Diameter BVA for Finer-Pitch, Low-Profile PoP
• Ongoing efforts to develop 1.0mm total stack-up height BVA PoP
• Process optimized to develop 1.5mil wire, thin mold cap, and exposed die
backside
<1.0 mm thickness
Exposed Die package
60µm mold gap
100µm mold gap
Process Step
Validation
Support
Vertical Wirebond
K&S
Film-assist Mold
Yamada
Plasma Clean
Nordson March
Solder Ball Attach
(0.24, 0.30, 0.40mm
pitch)
Shibuya
Singulation
Hanmi
PoP Stacking
UIC
OSAT:
STS (KR)
Ongoing HVM Validation Activity with Equipment and Assembly Suppliers
TMV
Minimum pitch
Package size
No. of IO
Specialized
Packaging Steps
Stacking
Reliability

BVA
0.35 mm (demonstrated),
0.3 mm (projected)
0.24 mm (demonstrated),
0.15 mm (projected)
14 mm x 14 mm x 1.2 mm
14 mm x 14 mm x 1.2 mm
256 (2 rows) 372 (3 rows)
432 (2 rows) 1020 (5 rows)
Molding, laser via drilling, cleaning,
solder deposit
Wire-bonding
SMT
SMT
<100 drops without underfill
>100 drops without underfill
BVA offers 1000+ IO with high aspect ratio interconnect within same package size
Technology
Value
• Stand-off issue eliminated: Wire-bond based
memory-logic interconnect
• 1000+ wide IO: 0.2 mm pitch capability
• Conventional equipment and process
• BVA PoP with 1020 IO logic-memory interface
successfully demonstrated at 0.24 mm pitch and
passed reliability tests
• More than 2X IO in the same package size
compared to competing solutions
• Utilizes existing assembly infrastructure and is
cost competitive
• High performance at low-cost
• Bridge technology available ahead of 3DIC

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